Reducing power in high-performance microprocessors

Tiwari, Vivek; Singh, Deo; Rajgopal, Suresh; Mehta, Gaurav; Patel, Rakesh; Baez, Franklin

doi:10.1145/277044.277227

Cited by 218 publications

(24 citation statements)

References 5 publications

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“…Each set stresses different parts of the processor: set B has the highest power consuming clock system, set C features power hungry caches, set D stresses the functional units, and set A is an average of the other three sets. The values in the table • E. Musoll have been partially obtained from some published data [Burd and Peters 1994;Dobberpuhl et al 1992;Gowan et al 1998;Meng et al 1995;Santhanam 1996;Scott et al 1998;Tiwari et al 1998] and from extrapolations when no information is available.…”

Section: Resultsmentioning

confidence: 99%

Speculating to reduce unnecessary power consumption

Musoll¹

2003

ACM Trans. Embed. Comput. Syst.

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The power consumption of current processors keeps increasing in spite of aggressive circuit design techniques and process shrinks. One of the reasons for this increase is the complexity of the microarchitecture required to achieve the performance that each processor generation demands. These techniques, such as branch prediction and on-chip level two caches, increase not only the power consumption of the committed instructions, but also the useless power associated with those block accesses that generate results that are not needed for the correct execution and commit of the instructions.In this work, the different accesses that a particular block receives are classified into four different components, based on whether the accesses are performed by instructions of the correct path or the wrong (mispredicted) path, and also based on whether the results of the accesses are needed or not for the correct execution of the instructions. Out of the four components, only one accounts for the useful accesses to the block, that is, accesses performed to correctly execute instructions that will be committed. The other three components account for the useless activity on the block. The simulations performed indicate that, if the useless power dissipation of a high-performance processor could be totally removed with no performance degradation, the overall processor power consumption would be reduced by as much as 65% compared to the same processor in which all the blocks are accessed every cycle.This work then proposes a microarchitectural technique that targets the reduction of the useless power dissipation. The technique consists of predicting whether the result of a particular block of logic will be useful in order to execute the instructions (no matter whether the instructions will be eventually committed or not). If it is predicted useless, then the block is disabled.A case example is presented where two blocks are predicted for low power: the on-chip L2 cache for instruction fetches and the branch target buffer (BTB). The IPC versus power-consumption design space is explored for a particular microprocessor architecture. Both the average and the peak power consumption are targeted. High-level estimations are done to show that it is plausible that the ideas described might produce a significant reduction in useless block accesses. As an example, 65% accesses to the L2 cache can be eliminated at a 0.2% IPC degradation, and about 5% accesses to the BTB can be saved at the penalty of 0.7% IPC reduction.

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Section: Resultsmentioning

confidence: 99%

Speculating to reduce unnecessary power consumption

Musoll¹

2003

ACM Trans. Embed. Comput. Syst.

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“…In large SoC systems, the design of a global clock tree for all function units is very expensive and can consume a significant portion of the power budget [8]. It is now generally agreed that the very large scale integration (VLSI) systems of the nanoscale era will not operate under the control of a single clock and will require asynchronous techniques [9].…”

Section: Asynchronous Communicationmentioning

confidence: 99%

A clock-less transceiver for global interconnect

Jiang

Wang

Sheng

et al. 2011

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

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High speed and low power transceivers start to be used for global interconnection in state-of-the-art System-on-Chips (SoCs). In traditional transceivers, the bandwidth is largely dependent on the clock rate. This paper presents a clock-less transceiver for global interconnect. The asynchronous transceiver makes the data rate only depend on the link delay and can be conveniently used with low swing scheme to create a high speed and low power communication system. The transceiver is demonstrated and simulated. The simulation results indicate that the transceiver can be used in high speed and low power global communications.

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“…NoC is an efficient on-chip communication architecture for SoC architectures that is structured, reusable, scalable, and has high performance [1] [2]. Nowadays, power issues are becoming of primary design constraints for even very high-end microprocessors.…”

Section: Introductionmentioning

confidence: 99%