Reducing power dissipation in FIR filters using the residue number system

Cardarilli, G.C.; Nannarelli, Alberto; Re, M.

doi:10.1109/mwscas.2000.951651

Cited by 39 publications

(26 citation statements)

References 5 publications

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“…The available time slack in the faster clusters (smaller moduli) allows to exchange HS with LL cells and reduce both the dynamic and static power dissipation. This is similar to what is done in [12] in the dual voltage approach.…”

Section: Low Power Fir Filterssupporting

confidence: 78%

“…By using isomorphisms, the product of the two residues is transformed into the sum of their indices which are obtained by an isomorphic transformation (see [12] for implementation detail). The modular multiplication on m i = 64 is obtained by the normal binary multiplication limited to the 5 least-significant bits.…”

Section: B Rns Fir Filtersmentioning

confidence: 99%

“…Figure 5 shows the implementation of a tap for a generic RNS prime modulus. The critical path for RNS filters in transposed form is the maximum delay in the tap for the slowest modulus t RN S = t modM U LT + t modADD + t REG that, for the implementation of Figure 5, is t RN S = t ISO + 2 · t modADD + t REG (see [12] for implementation detail).…”

Section: B Rns Fir Filtersmentioning

confidence: 99%

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Low Power and Low Leakage Implementation of RNS FIR Filters

Cardarilli¹,

Re²,

Nannarelli³

et al.

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

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Abstract-The CMOS technology scaling is leading to the integration of ever more complex systems on silicon. On the other hand, the shrinking of the devices and the reduction of the supply voltage have significantly increased the static power dissipation, that in power budgets of nanometer technologies, cannot be neglected any longer. In this work, we take advantage of the properties of the Residue Number System (RNS) to implement FIR filters with reduced static and dynamic power consumption. The results show that the RNS filters offer a reduction of 50% in static power dissipation and a total power reduction of 40% with respect to the corresponding conventional filters. I. INTRODUCTIONThe objective of the work described in [1] was the comparison of the power consumption of Finite Impulse Response (FIR) filters implemented in the traditional two's complement system (TCS) and in the Residue Number System (RNS). The work in [1] took into account the dynamic power dissipation, which was by far the dominant portion of the energy consumed a few years ago.With the technology scaling, and the increased transistor's leakage due to sub-threshold currents, also the static power dissipation starts to play an important role in today's power budgets. Moreover, the increasing smaller CMOS transistors allow the hardware implementation of extra functions that before were executed in software, and the migration of complex system to portable devices. Because of the implementation of digital filters in ultra low power processors, such as the one used in tiny systems with limited available power, it is important the static power due to leakage is characterized and, possibly, reduced.To have an idea of the impact of the device's leakage on power dissipation, we implemented a multiplier, which is the basic block of a FIR filter, in a 0.18 µm, a 0.12 µm and in a 90 nm library. We used the same timing constraint, the delay of 25 inverters with fanout of 4 (a standard measure of delay across different technologies) in their respective libraries. The results, shown in Table I, indicate that the power dissipation due to leakage P stat increases both in absolute value and as the percentage of the overall power dissipation P T OT . By comparing the 0.18 µm and the 90 nm multipliers, we notice that P T OT has decreased of about 70% (mostly due to the scaling of V DD ), but the static part P stat has increased 14 times and its contribution to the total 40 times. Moreover, for the 90 nm implementation, if the multiplier is used as often as 1% of the processor usage time the static power dissipation becomes dominant. Therefore, the design

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Section: Low Power Fir Filterssupporting

confidence: 78%

Section: B Rns Fir Filtersmentioning

confidence: 99%

Section: B Rns Fir Filtersmentioning

confidence: 99%

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Low Power and Low Leakage Implementation of RNS FIR Filters

Cardarilli¹,

Re²,

Nannarelli³

et al.

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

Self Cite

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“…In 2000, we presented the RNS as an effective technique to lower the power consumption in DSP applications [5]: the RNS implementation of a FIR filter showed to be about half smaller and power hungry then the TCS filter when designed at the same timing constraint.…”

Section: A Asic Platformsmentioning

confidence: 99%

“…Over the years, several applications in Digital Signal Processing (DSP), such as digital filters, have benefit from the RNS implementation, e.g., [3], [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Twenty years of research on RNS for DSP: Lessons learned and future perspectives

Albicocco

Cardarilli

Nannarelli

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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Abstract-In this paper, we discuss a number of issues emerged from our twenty-year long experience in applying the Residue Number System (RNS) to DSP systems.In early days, RNS was mainly used to reach the maximum performance in speed. Today, RNS is also used to obtain powerefficient (tradeoffs speed-power) and reliable systems (redundant RNS). Advances in microelectronics and CAD tools play an important role in favoring one technology over another, and a winning choice of the past may become at disadvantage today.In this paper, we address a number of factors influencing the choice of RNS as the winning solution. From technology platforms (ASIC and FPGA), to issue related to modern design tools, from cost of memory, to cost of wiring, from power dissipation to thermal issues. Moreover, we mention how RNS can be helpful in implementing reliable architectures (fault detection and correction) in future VLSI systems.

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RNS Applications in Digital Signal Processing

Cardarilli

Nannarelli

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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The Residue Number System (RNS) as an alternative to binary representation in digital systems has been studied extensively in the last decades [1,26]. The attractive feature of the RNS is that for operations such as addition and multiplication, a large dynamic range (bit-width) can be divided into sub-ranges of reduced bit-width by splitting the datapath in independent parallel channels where the operations can be executed faster (shorter carry propagation) [26].The main drawback is that converters are required to interface an RNS datapath to the conventional systems based on binary representation, so the use of RNS is justified when the number of operations to be performed in RNS, without conversions, is significant.Over the years, several applications in Digital Signal Processing (DSP), such as digital filters, have benefit from the RNS implementation, e.g., [8,11,15,24].Here, we describe the RNS implementation of a number of DSP algorithms by comparing their performance (clock rate, area, and power dissipation) to the same algorithms implemented in the traditional two's complement number system (TCS), and discussing some trade-offs.In Sect. 8.2, we recall the main RNS concepts to introduce the notation used in the chapter.In Sect. 8.3, we explain the main criteria to choose the RNS base and discuss same trade-offs in choosing the right base for a given application.

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Reducing power dissipation in FIR filters using the residue number system

Cited by 39 publications

References 5 publications

Low Power and Low Leakage Implementation of RNS FIR Filters

Low Power and Low Leakage Implementation of RNS FIR Filters

Twenty years of research on RNS for DSP: Lessons learned and future perspectives

RNS Applications in Digital Signal Processing

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