Reducing power consumption during test application by test vector ordering

Girard, Patrick; Landrault, C.; Pravossoudovitch, S.; Severac, Daniel

doi:10.1109/iscas.1998.706917

Cited by 92 publications

(74 citation statements)

References 2 publications

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“…Table 9 shows the comparison of ASA of the proposed work with Sokolov et al (2005) and Girard et al (1998). ASA is observed to be reduced for most of the benchmark circuits as compared to the results mentioned in Sokolov et al (2005) and Girard et al (1998). Table 9 Comparison of ASA Circuit MT-fill Sokolov et al (2005) Girard et al (1998 …”

Section: Results and Comparisonmentioning

confidence: 92%

“…This is because in MT fill the X-bits are filled on the basis of specified bit on the same bit position in the previous test vector. Table 9 shows the comparison of ASA of the proposed work with Sokolov et al (2005) and Girard et al (1998). ASA is observed to be reduced for most of the benchmark circuits as compared to the results mentioned in Sokolov et al (2005) and Girard et al (1998).…”

Section: Results and Comparisonmentioning

confidence: 93%

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A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Mohan

Anita

2016

IJMMNO

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This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing.Keywords: relaxation; zero suppressed binary decision diagram; ZBDD; test power.Reference to this paper should be made as follows: Mohan, N. and Anita, J.P. (2016) 'A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults', Int.

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Section: Results and Comparisonmentioning

confidence: 92%

Section: Results and Comparisonmentioning

confidence: 93%

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Mohan

Anita

2016

IJMMNO

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“…A simple alternative solution for minimizing power consumption during scan testing is to use test vector ordering or scan cell ordering techniques. Test vector ordering has been investigated in [7,8,9] with the objective to define the order in which test vectors of a deterministic test set have to be applied to the circuit or core under test (CUT) to minimize the overall switching activity. Scan cell ordering bas been investigated only in [7], where two heuristics are proposed to determine the order in which the scan flip-flops of a given scan chain have to connected a random ordering heuristic and a simulated annealing algorithm.…”

Section: Imentioning

confidence: 99%

Bit Swapping and Cell Ordering on Finding Faults in Test Pattern Generation using BIST

Anandhi¹

2018

IJRASET

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Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/ maximal pattern-pair coverage for sequential circuit has been derived. A new low power weighted pseudorandom test pattern generator using weighted test-enable signals is proposed using a new clock disabling scheme .It supports both pseudorandom testing and deterministic BIST. To implement the low power BIST scheme, a design-for-testability (DFT) architecture is presented. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is used by disabling a part of scan chains.A novel low-power bit-swapping LFSR (BS-LFSR) is used to minimize the transistions, while keeping the randomness almost similar. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycles (or) while scanning out a response to a signature analyzer. These techniques have a substantial effect on average and peak power compared to the existing approach. Keywords: Bit swapping, Scan chain reordering, Delay fault and Stuck-at-Fault, Design for testability and test pattern generation. I.INTRODUCTION Power dissipation during external scan testing, i.e. from an ATE (Automatic Test Equipment). Scan architectures are very popular and are commonly used to test digital circuitry in integrated circuits (ICs) or cores. However, scan-based architectures are expensive in power consumption as each test pattern requires a large number of shift operations with a high circuit activity [1]. Of course, it is always possible to reduce average power during scan testing by simply scanning at a lower frequency. However, this increases test application time. Another solution is to add logic to hold the output of the scan cells at a constant value during scan shifting [2]. A simple alternative solution for minimizing power consumption during scan testing is to use test vector ordering or scan cell ordering techniques. Test vector ordering has been investigated in [7,8,9] with the objective to define the order in which test vectors of a deterministic test set have to be applied to the circuit or core under test (CUT) to minimize the overall switching activity. Scan cell ordering bas been investigated only in [7], where two heuristics are proposed to determine the order in which the scan flip-flops of a given scan chain have to connected a random ordering heuristic and a simulated annealing algorithm. Experimental results on small benchmark circuits show that scan cell ordering can reduce test power by 10.25% with no change in terms of fault coverage and test length. Larger benchmark circuits have not been experimented because they are intractable with the pro...

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“…It is seen that the number of transitions are reduced greatly by the minimum transition fill technique as compared to the other fill techniques. Table 11 shows the comparison of the proposed work in terms of the average switching activity (ASA) with Girard et al (1998). ASA is given by the ratio of the number of transitions obtained due to internal switching activity to the total number of test patterns.…”

Section: Test Power Reductionmentioning

confidence: 99%

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Anita

Sudheesh

2016

IJHPSA

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An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing.

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Reducing power consumption during test application by test vector ordering

Cited by 92 publications

References 2 publications

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Bit Swapping and Cell Ordering on Finding Faults in Test Pattern Generation using BIST

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

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