Reducing memory interference in multicore systems via application-aware memory channel partitioning

Abstract

Main memory is a major shared resource among cores in a multicore system. If Technical Report No. 2011-002 (June 3, 2011 system configurations show that this integrated memory partitioning and scheduling approach provides better system performance than MCP and four previous memory scheduling algorithms employed alone. Averaged over 240 workloads on a 24-core system with 4 memory channels, IMPS improves system throughput by 11.1% over an application unaware scheduler and 5% over the current best scheduling policy, while incurring much lower hardware complexity than the latter.

Bounding memory interference delay in COTS-based multi-core systems

“…The row-interleaved policy, however, can significantly increase the memory access latency in a multi-core system [26,22,13]. For instance, multiple tasks running simultaneously on different cores may be mapped to the same DRAM banks.…”

Going vertical in memory management: Handling multiplicity by multi-policy

“…Previous research efforts [12,29] show that contention can significantly degrade the overall system performance and many solutions have been proposed to mitigate the contention problems.…”

“…Prior efforts [8,10,15,16,17,26,29,30,31] demonstrate that horizontal partitioning on memory or LLC is effective in eliminating inter-program interference and improving performance. With vertical partitioning and, more generally, our partitioning policy space, one important question is whether the benefits from the horizontal memory and cache partitioning can be accumulated (i.e., should we go vertical in partitioning?…”

“…At the main memory level, Prashanth et al [29] proposes DRAM channel partitioning that requires hardware and system modifications to segregate data from different threads into different channels to eliminate interference. Park et al [18] adopt a random allocation algorithm to scatter allocated pages to multiple banks to avoid conflicts for multithreaded workloads.…”

“…Several recent solutions attempt to segregate applications with different memory resources requirements by horizontally partitioning either main memory (DRAM banks) [10,16,17,29] or cache [15,24,30,31,32] into exclusive slices. These approaches avoid interference for programs with small memory footprints but might hamper performance of larger workloads by effectively reducing capacity.…”