Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis

Guzma, Vladimir; Pitkänen, Teemu; Takala, Jarmo

doi:10.1109/issoc.2010.5625536

Cited by 5 publications

(7 citation statements)

References 11 publications

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“…Once the binaries for different sizes of loop unrolling threshold were generated, we analyzed them to find simple loops suitable for storing in the instruction buffer, as well as the number of iterations those loops perform for our sample input using instruction trace [9]. We also find the most beneficial loop; one where the number of iterations multiplied by number of instruction is greater than for any other candidate loop.…”

Section: Experimental Setup and Measurement Methodologymentioning

confidence: 99%

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Effects of loop unrolling and use of instruction buffer on processor energy consumption

Guzma

Pitkänen

Takala

2011

2011 International Symposium on System on Chip (SoC)

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In the area of Embedded Systems, instruction memories are one of the critical components consuming significant amounts of energy. Existence of a relation between size of the compiled program, and consequently required size of the instruction memory, and the compiler optimization flags is wellknown. In particular, loop transformations such as loop unrolling, while having potential to increase performance dramatically, often cause unreasonable growth in the size of the required instruction memory, causing loss of benefit of lower cycle count from overall system energy point of view.One method how to decrease energy consumption of the memories is use of instruction buffers. Often executed loops are stored in the buffer and executed from there, while main memory is not read.In this paper, we show how the compiler flag, controlling loop unrolling, influences the structure of the loops in the program. While unrolling improves performance, unrolled loops can disappear from the program completely, or grow to unreasonable size where use of instruction buffer brings no benefits from the energy point of view.978-1-4577-0672-1/11/$26.00 c 2011 IEEE

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Section: Experimental Setup and Measurement Methodologymentioning

confidence: 99%

“…Our previous work [9] describes actual methods how to find out suitable size of the instruction buffer for specific application by using after code generation analysis and trace results from the simulation.…”

Section: Introductionmentioning

confidence: 99%

Effects of loop unrolling and use of instruction buffer on processor energy consumption

Guzma

Pitkänen

Takala

2011

2011 International Symposium on System on Chip (SoC)

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“…In our earlier work [9] we explored benefits of introducing instruction buffer sized specifically for the most often used simple loop. This loop type, visible in Figure 1 as starting from node Entry 3, contained only single basic block, ending with the loop predicate test.…”

Section: Characteristic Loop Typesmentioning

confidence: 99%

“…Starting with Entry 7 and Entry 8. Both those loops can be buffered as was presented in our earlier work [9]. Adding loop starting with Entry 9 therefore increases the number of instruction executed from the buffer.…”

Section: Characteristic Loop Typesmentioning

confidence: 99%

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Instruction buffer with limited control flow and loop nest support

Guzma

Pitkänen

Takala

2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from the loop or early return to the beginning of the loop). We also show how analysis of loop nests can decrease the number of times loop body is copied from memory into the buffer. Our results show that in case of favorable loop nest, we can execute all but initial loop iterations from the instruction buffer, keeping instruction memory in the deselect mode.

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Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Žádník

Takala

2019

ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis

Cited by 5 publications

References 11 publications

Effects of loop unrolling and use of instruction buffer on processor energy consumption

Effects of loop unrolling and use of instruction buffer on processor energy consumption

Instruction buffer with limited control flow and loop nest support

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

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