Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

Kim, Suhwan; Choi, Chang Jun; Jeong, Deog‐Kyoon; Kosonocky, Stephen; Park, Sung Bae

doi:10.1109/ted.2007.911067

Cited by 44 publications

(29 citation statements)

References 15 publications

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“…The voltage difference between Vvss1 and the gate node of M2 is decreased from around Vdd to n2 voltage which makes Ig2 exponentially decrease according to gate leakage equation. During the short mode-transition time from sleep to active, the conventional power switch suffers from rush-thru current and large wake-up time [3]. In order to overcome this problem, it is suggested that the virtual ground voltage is gradually decreased using a new structure as shown in Fig.…”

Section: Power Switch Implementationmentioning

confidence: 99%

Power switch implementation for low voltage digital circuits

Kim

2013

IEICE Electron. Express

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This letter presents a novel power switch structure using only low threshold voltage MOSFETs to extend the power switch to ultra-low voltage region. The proposed structure deploys seriesconnected low-Vth footers with two virtual ground ports and selectively chooses the logic cells for connecting to each virtual ground port according to the delay criticality. Moreover, additional circuitries are designed to reduce not only sub-threshold leakage current, but also gate-tunneling leakage and to reduce wake-up time and wake-up fluctuation compared to the conventional power switch. The total power switch size of the proposed power switch structure including the additional circuits is less than the conventional one. The simulation results show that the proposed power gating structure has advantage of low leakage power, small footer size, and low wake-up time, but high-performance, low wake-up fluctuation, wake-up power for inverter chains and ISCAS85 benchmark circuits at 1.1 V and 0.6 V VDD which are designed using 45 nm CMOS technology.

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Section: Power Switch Implementationmentioning

confidence: 99%

Power switch implementation for low voltage digital circuits

Kim

2013

IEICE Electron. Express

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“…The sleep time of the circuit is considered to be long enough such that the internal node will be charged to a steady value [3,4,5]. This steady value is then used to estimate the leakage savings, wake-up time, ground-bounce noise and so on.…”

Section: Figure 1: Virtual Ground Of Ground Gatingmentioning

confidence: 99%

Dynamic virtual ground voltage estimation for power gating

Vemuri

Jone

2008

Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design - ISLPED '08

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With the technology moving into the deep sub-100nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG) as the key to make critical design trade-offs for power gating. We develop an accurate model to estimate the dynamic VVG value of a circuit block as a function of time after its ground is gated. Experimental results show that the model has less than 1% average error compared with HSPICE results. The CAD tool implemented based on the model has a 100× speedup over HSPICE.

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“…In measuring this latency [9], the inductive noise due to clock gating is effectively excluded, since the performance degradation due to the Fig. 4.…”

Section: Ground Bounce Noise Reductionmentioning

confidence: 99%

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

Lee¹,

Lee²,

Woo

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudorandom manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

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Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

Cited by 44 publications

References 15 publications

Power switch implementation for low voltage digital circuits

Power switch implementation for low voltage digital circuits

Dynamic virtual ground voltage estimation for power gating

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

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