Reducing DRAM latencies with an integrated memory hierarchy design

Lin, Wey Jinq; Reinhardt, Steven K.; Burger, Doug

doi:10.1109/hpca.2001.903272

Cited by 54 publications

(12 citation statements)

References 22 publications

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“…Figure 3 illustrates one rank interleaving address mapping. Several Studies have examined more involved address mappings with the objective of reducing SDRAM row conflicts [3,16,18,19]. Wei-fen Lin [18] pointed out that address mappings affect performance significantly and proposed an address mapping scheme that XORs the device and bank index with the lower bits of the row address.…”

Section: Related Workmentioning

confidence: 99%

“…Several Studies have examined more involved address mappings with the objective of reducing SDRAM row conflicts [3,16,18,19]. Wei-fen Lin [18] pointed out that address mappings affect performance significantly and proposed an address mapping scheme that XORs the device and bank index with the lower bits of the row address. This mapping retains the contiguousaddress striping properties across banks at the granularity of a SDRAM row and distributes the blocks that map to a given cache set evenly across the banks.…”

Section: Related Workmentioning

confidence: 99%

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The bit-reversal SDRAM address mapping

Shao

Davis

2005

Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems - SCOPES '05

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The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bitreversal, is described and experimentally compared against known methods. The bit-reversal address mapping increases SDRAM row hit rate from 43% to 66% by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26% 29% over other methods, resulting in a 11.7%-13.5% reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

The bit-reversal SDRAM address mapping

Shao

Davis

2005

Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems - SCOPES '05

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“…Lin, et. al [20] mitigate the negative effects of prefetching on performance by prefetching only when the memory bus is idle (to reduce contention), and prefetching to lower replacement priorities than demand misses (to reduce cache pollution). Ki and Knowles [31] used extra cache bits to increase prefetching's accuracy.…”

Section: Related Workmentioning

confidence: 99%

Interactions Between Compression and Prefetching in Chip Multiprocessors

Alameldeen

Wood

2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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In chip multiprocessors (CMPs), multiple cores compete for shared resources such as on-chip caches and off-chip pin bandwidth. Stride-based hardware prefetching increases demand for these resources, causing contention that can degrade performance (up to 35% for one of our benchmarks).In this paper, we first show that cache and link (off-chip interconnect) compression can increase the effective cache capacity (thereby reducing off-chip misses) and increase the effective off-chip bandwidth (reducing contention). On an 8-processor CMP with no prefetching, compression improves performance by up to 18%for commercial workloads. Second, we propose a simple adaptive prefetching mechanism that uses cache compressions extra tags to detect useless and harmful prefetches. Furthermore, in the central result of this paper, we show that compression and prefetching interact in a strong positive way, resulting in combined performance improvement of 10-51% for seven of our eight workloads.

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“…Based on program locality principle and costeffective of various kinds of storage media, memory hierarchy architecture has been proposed to resolve this issue [5][6][7]. A typical memory hierarchy is cache-based, as cache is the key memory level to capture program locality and reduce off-chip memory access requirements and latency [8][9].…”

Section: Introductionmentioning

confidence: 99%

Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM Memory Hierarchy Architecture

Ren

Tang

et al. 2010

2010 IEEE 12th International Conference on High Performance Computing and Communications (HPCC)

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As a fast on-chip SRAM managed by software (the application and/or compiler), Scratchpad Memory (SPM) is widely used in many fields. This paper presents a SimpleScalar-based multi-level SPM memory hierarchy architecture simulator Sim-spm. We simulate the hardware of the multi-level SPM memory hierarchy successfully by extending Sim-outorder, which is an out-of-order simulator from SimpleScalar. Through the simulating memory method, the simulation framework of the multi-level SPM memory hierarchy has been built under the existing ISA (Instruction Set Architecture), which largely reduces the requirement to modify the existing compiler. The experimental results show that Sim-spm can accurately simulate the running state of the processor with a multi-level SPM memory hierarchy architecture, and it has a good prospect for the research of multi-level SPM memory hierarchy architecture.

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Reducing DRAM latencies with an integrated memory hierarchy design

Cited by 54 publications

References 22 publications

The bit-reversal SDRAM address mapping

The bit-reversal SDRAM address mapping

Interactions Between Compression and Prefetching in Chip Multiprocessors

Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM Memory Hierarchy Architecture

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