Reducing Crossbar Costs in the Match-Action Pipeline

Zolfaghari, Hesam; Rossi, Davide; Nurmi, Jari

doi:10.1109/hpsr.2019.8808105

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…Different designs may opt for alternative solutions based on their specific needs and trade-offs. By limiting the unit and range of selection fields, resource consumption can be effectively reduced while ensuring rationality [22]. In the work of [23], an efficient header analysis and field extraction architecture is proposed for FPGA-based network applications.…”

Section: Related Workmentioning

confidence: 99%

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

Song,

Lu,

Guo

2024

Micromachines

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As the key module of programmable switches or the SmartNIC card, the packet processing pipeline undertakes the task of packet forwarding and processing. However, the current pipeline for the FPGA-based SmartNIC is inflexible, and the related reconfigurable commercial device designs are closed-source. To solve this problem, this paper proposes a high-performance reconfigurable pipeline design, which has fully reconfigurable match-action units, supporting various network functions by its flexible reconfiguration. The fields of the match key and the size of the match table can be reconfigured without recompiling the HDL code or modifying the hardware. The processing rules and action instructions for the pipeline can be dynamically installed by the configuration module at runtime. We implement our design on the Xilinx Alveo U200 board with a Virtex UltraScale+ XCU200-2FSGD2104E FPGA and show that the designed pipeline supports fast reconfiguration to implement new network functions and that the throughput of the designed pipeline reaches 100 Gbps with low latency.

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Section: Related Workmentioning

confidence: 99%

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

Song,

Lu,

Guo

2024

Micromachines

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Section: Model Descriptionmentioning

confidence: 99%

“…In this article, we employ a zero-extended crossbar [ 30 ], which is capable of reading data of different widths from its input and output data in a larger fixed-width format, with zero-padding unused bits. By utilizing two-stage crossbar switches with zero scalability, our approach leads to a remarkable 52.7% reduction in area and a significant 46.7% decrease in power consumption compared to conventional bit-level interconnect schemes [ 30 ]. The advantage of this reduction is derived from the ability of the crossbar switch to handle varying data lengths without requiring additional resources for expansion, unlike bit-level interconnect schemes that tend to be more complex and resource intensive.…”

Section: Model Descriptionmentioning

confidence: 99%

The Design of a Dynamic Configurable Packet Parser Based on FPGA

Sun

Guo

2023

Micromachines

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To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.

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“…Therefore, it is desirable to evaluate the possibility of optimizations for saving area. In [35] different alternatives for field extractors are compared. We consider two optimization strategies.…”

Section: Inputs To Field-and State-modifiersmentioning

confidence: 99%

Flexible Software-Defined Packet Processing Using Low-Area Hardware

et al. 2020

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Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture.

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Reducing Crossbar Costs in the Match-Action Pipeline

Cited by 4 publications

References 7 publications

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC

The Design of a Dynamic Configurable Packet Parser Based on FPGA

Flexible Software-Defined Packet Processing Using Low-Area Hardware

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