Reducing Context Switch Overhead with Compiler-Assisted Threading

Jääskeläinen, Pekka; Kellomäki, Pertti; Takala, Jarmo; Kultala, Heikki; Lepisto, M.

doi:10.1109/euc.2008.181

Cited by 7 publications

(7 citation statements)

References 7 publications

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“…After the exploration process completes, the designer is able to select the architecture based on restrictions given on speed, area or energy. While in this work we concentrate on creation of pairs of applications that works in sequence, the TCE framework also supports compiler assisted multithreading [18].…”

Section: B Automated Application-specific Instruction Set Extension mentioning

confidence: 99%

An integrated ASIP design flow for digital signal processing applications

Guzma

Bhattacharyya

Kellomäki

et al. 2008

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

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Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can expose the high level structure of applications that is useful for various kinds of optimizing design transformations. One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications. In this paper, we develop an integration of SDF-and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations. We also explore an approach to ASIP implementation in terms of "critical" and "non-critical" applications, which allows designers to tune the degree of specialization for a targeted ASIP. Our results show that single ASIP processor tuned for pair of critical applications saves 26% to 50% of area required for implementations of two applications on separate ASIPs and noncritical applications runs on such processor with in worst case 4.5% overhead for our selection of benchmarks.

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Section: B Automated Application-specific Instruction Set Extension mentioning

confidence: 99%

An integrated ASIP design flow for digital signal processing applications

Guzma

Bhattacharyya

Kellomäki

et al. 2008

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

Self Cite

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“…The migration rate is likely to increase in a virtualization server environment, where logical CPUs are often highly oversubscribed by VCPUs for applications such as server consolidation and virtual desktops infrastructure deployment. For example, the vConsolidate benchmark [8] developed by Intel to measure the performance of a system running consolidated workloads has six consolidated stack units (CSU) consisting of a total of 48 VCPUs running in a two-socket server with a total 16 [13] proposed co-operative multithreading so context switches occur in places that require a minimal amount of processor state to be saved. Ditzel [14] described how SPARC TM Version 9 has improved context switching direct overhead by saving and restoring fewer registers during a context switch.…”

Section: Chapter 2: Related Workmentioning

confidence: 99%

“…While some research has been done in estimating the impact/overhead of context switch from cache misses and branch miss-predictions, there are only few [13,14] articles on the characterization of the impact of misses due to a context switch coupled with migration.…”

Section: Chapter 1: Introductionmentioning

confidence: 99%

Reducing Migration-Induced Misses in an Over-Subscribed Multiprocessor System

Reza

Byrd

2013

Parallel Process. Lett.

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In a large multiprocessor server platform using multicore chips, the scheduler often migrates a thread or process, in order to achieve better load balancing or ensure fairness among competing scheduling entities. Each migration incurs a severe performance impact from the loss of cache and Translation Lookaside Buffer (TLB) footprints and subsequent higher cache misses and page walks. Such impact is likely to be more severe in virtualized environments, where high over-subscription of CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment, causing frequent migrations and context switches. We demonstrate the performance benefit of preserving a portion of L2 cache—in particular, MRU cache lines—and warming the destination L2 cache by prefetching those cache lines under different migration scenarios. We observed a 1.5-27% reduction in CPI (cycles per instruction) following a migration. We also study the effectiveness of preserving TLB entries over a context switch or migration.

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“…Two papers employed a transpiler that translates from one language to another -one from Lustre to OCaml (Jahier 2016) and one from a synchronous extension of C to standard C(Karpinski and Cahill 2007). One paper (Fritzsche and Siemers 2010) used a precompiler, and one paper(Jääskeläinen et al 2008) provided a new compiler optimisation phase.Two studies called out to another language to implement the coroutines: one(Park et al 2015), wri en in the Lua language (DeMoura et al 2004), directly manipulated the hosting environment through the C API; another(Khezri et al 2008) used non-portable assembly language. e results are summarised inFigure 2b…”

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confidence: 99%

A Survey of Asynchronous Programming Using Coroutines in the Internet of Things and Embedded Systems

Belson

Holdsworth

Wang

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Many Internet of ings and embedded projects are event-driven, and therefore require asynchronous and concurrent programming.Current proposals for C++20 suggest that coroutines will have native language support. It is timely to survey the current use of coroutines in embedded systems development.is paper investigates existing research which uses or describes coroutines on resource-constrained platforms. e existing research is analysed with regard to: so ware platform, hardware platform and capacity;use cases and intended bene ts; and the application programming interface design used for coroutines. A systematic mapping study was performed, to select studies published between 2007 and 2018 which contained original research into the application of coroutines on resource-constrained platforms. An initial set of 566 candidate papers, collated from on-line databases, were reduced to only 35 a er lters were applied, revealing the following taxonomy. e C & C++ programming languages were used by 22 studies out of 35.As regards hardware, 16 studies used 8-or 16-bit processors while 13 used 32-bit processors. e four most common use cases were concurrency (17 papers), network communication (15), sensor readings (9) and data ow (7). e leading intended bene ts were code style and simplicity (12 papers), scheduling (9) and e ciency (8). A wide variety of techniques have been used to implement coroutines, including native macros, additional tool chain steps, new language features and non-portable assembly language. We conclude that there is widespread demand for coroutines on resource-constrained devices. Our ndings suggest that there is signi cant demand for a formalised, stable, well-supported implementation of coroutines in C++, designed with consideration of the special needs of resource-constrained devices, and further that such an implementation would bring bene ts speci c to such devices.

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Reducing Context Switch Overhead with Compiler-Assisted Threading

Cited by 7 publications

References 7 publications

An integrated ASIP design flow for digital signal processing applications

An integrated ASIP design flow for digital signal processing applications

Reducing Migration-Induced Misses in an Over-Subscribed Multiprocessor System

A Survey of Asynchronous Programming Using Coroutines in the Internet of Things and Embedded Systems

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