Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning

Agnesina, Anthony; Lepercq, Etienne; Escobedo, Jose Pablo; Lim, Sung Kyu

doi:10.1109/iccad45719.2019.8942091

Cited by 2 publications

(3 citation statements)

References 10 publications

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“…Some works employ ML to select the tool parameters. Agnesina et al [41] targeted FPGA place&route and built several models with the goal of accelerating compilation time. These models classify netlists into easy and hard classes, predict the best tool parameters, or predict compile time.…”

Section: Physical Designmentioning

confidence: 99%

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

Rapp

Amrouch

Lin

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in computer-aided design (CAD) that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions.

show abstract

Section: Physical Designmentioning

confidence: 99%

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

Rapp

Amrouch

Lin

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…ML is used in some works to select the tool parameters. With the aim of speeding up compilation time, [38] target FPGA place & route and construct many models. These models divide netlists into simple and complex categories, anticipate the optimal tool parameters, or predict compile times.…”

Section: Figure 20 Routenet Model [33]mentioning

confidence: 99%

“…The machine learning framework enables proper compilation techniques as well as accurate handling of runtime-intensive netlists. By adjusting the wall-time, [38] derives a practical method to enhance the trade-off between compile time and the number of jobs. By scheduling runs on the server grid optimally, ML models integrated into the proposed emulation system demonstrate that they can lower compilation costs.…”

Section: Figure 20 Routenet Model [33]mentioning

confidence: 99%

Application of Machine Learning to Physical Design

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Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning

Cited by 2 publications

References 10 publications

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

Application of Machine Learning to Physical Design

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