Reduced-state sequence detection with convolutional codes

Anderson, John B.; Offer, E.

doi:10.1109/18.335914

Cited by 40 publications

(10 citation statements)

References 9 publications

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“…Consider a VD for a Convolutional code with a constraint length k, where each state receives P candidate paths. If the branch metrics are calculated based on the Euclidean distance [3], the optimal PM becomes the minimum value of all the PMs. The minimum Pre-computation steps are shown below.…”

Section: Pre-computation Methodsmentioning

confidence: 99%

An Efficient Low Power Viterbi Decoder Design using T-algorithm

SridharReddy¹,

Nagarjuna²,

Kumar³

2013

IJCA

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This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. It implements the viterbi decoder using T-algorithm for decoding a bit-stream encoded by a corresponding forward error correction convolutional encoding system. A lot of digital communication systems incorporated a viterbi decoder for decoding convolutionally encoded data. The viterbi decoder is able to correct errors in received data caused by channel noise. We proposed an architecture implementing a Viterbi Decoder with Talgorithm deployed with threshold generator unit and purge unit to reduce the number of states which reduce power consumption. We propose modified architecture for the survivor Metric Unit to reduce the memory Access power during the trace back operation. The proposed viterbi decoder is carried out for rate-1/2 with a standard constraint length 7. The Synthesis results will be done using cadence RTL Encounter Tool. For ASIC synthesis, we use TSMC 45-nm CMOS Process. The architecture which reduces the complexity and power Consumption by as much as 70% without effecting the decoding speed.

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Section: Pre-computation Methodsmentioning

confidence: 99%

An Efficient Low Power Viterbi Decoder Design using T-algorithm

SridharReddy¹,

Nagarjuna²,

Kumar³

2013

IJCA

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“…A bus configuration satisfies a slice requirement if and only if (2) Proof ( ): The proof is by induction on the value of the sum . We show that, given and , if Inequality (2) holds for all , then for each global data transfer in , there exists a distinct bus in that can perform it.…”

Section: B Ilp Formulationmentioning

confidence: 99%

Design of a 20-mb/s 256-state Viterbi decoder

Liu

Papaefthymiou

2003

IEEE Trans. VLSI Syst.

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The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data transfer oriented design methodology to implement a low-power 256-state rate-1/3 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the register-transfer level (RTL) implementation, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 m standard cell library, our decoder achieves a throughput of 20 Mb/s in simulation and dissipates only 0.45 W.

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“…The number of states is reduced by using hard estimates either for some state components (i.e., reduce the number of states by reducing in ) or for the group where the state components belong (i.e., reduce for some components). In the first category, the most prevalent method is delayed-decision-feedback sequence estimation (DDFSE) [1] while in the second category belong schemes like those in [2] and [3]. The sequence equalization methods produce hard decisions at the equalizer output and again may suffer from error propagation effects.…”

Section: Introductionmentioning

confidence: 99%

“…Several papers such as [1]- [3] proposed reduced-state sequence equalization methods. The estimator uses a Viterbi algorithm with decision feedback to search a reduced-state trellis.…”

Section: Introductionmentioning

confidence: 99%

Prefiltered space-time M-BCJR equalizer for frequency-selective channels

Fragouli

Al-Dhahir

Diggavi

et al. 2002

IEEE Trans. Commun.

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Abstract-This paper addresses the problem of soft equalization for space-time-coded transmissions over frequency-selective fading channels. The structure of the space-time code is embedded in the channel impulse response for efficient joint equalization and decoding. The proposed equalization/decoding approach uses a prefilter to concentrate the effective channel power in a small number of taps followed by a reduced-complexity maximum a posteriori probability (MAP) equalizer/decoder to produce soft decisions. The prefilter introduces residual intersymbol interference which degrades the performance of MAP when applied to the trellis of the shortened channel. However, the shape of the overall shortened channel impulse response allows the -algorithm to approximate the prefiltered MAP performance with a small number of states. Based on this general framework, we investigate several enhancements such as using different prefilters for the forward and backward recursions, concatenating two trellis steps during decoding, and temporal oversampling. The performance is evaluated through simulations over the EDGE typical urban channel.

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Reduced-state sequence detection with convolutional codes

Cited by 40 publications

References 9 publications

An Efficient Low Power Viterbi Decoder Design using T-algorithm

An Efficient Low Power Viterbi Decoder Design using T-algorithm

Design of a 20-mb/s 256-state Viterbi decoder

Prefiltered space-time M-BCJR equalizer for frequency-selective channels

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