Reduced implementation of D-type DET flip-flops

Abstract

One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FF's) in VLSI systems design is the number of transistors required. In this paper two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FF's). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FF's in VLSI systems design.

Low-power sequential circuit design using T flip-flops

“…Therefore, power dissipation caused by the clock's rising edge is wasteful. For this reason, Double-Edge Triggered (DET) flip-flops have been developed which switch at both the falling and the rising edges of the clock (Unger 1981, Lu and Ercegovac 1990, Afghahi and Yuan 1991, Gago et al 1993, Hossain et al 1994, Pedram et al 1997. Consequently, the clock frequency can be reduced by half while keeping the same data rate, resulting in 50% power savings in the flip-flops.…”

A new design of double edge triggered flip-flops

“…[5,7] The maximum clock frequency for DET flip-flop is measured to be 450MHz, however, its maximum data rate should be doubled as shown in Table 1. A comparison of the simulation result with ones reported in Refs. [4,6,7] are listed in Table 2. Which shows that our design has a simpler structure, lower delay time and higher maximum date rate.…”

“…We should point out that the technology used in Refs. [4], [6], [7] are 2μ, 1.5μ, and 2μ, respectively. Besides, all MUXs used in Ref.…”

“…Results are given in table 3, where the design in Ref. [6] has been omitted since it requires transistor sizing in the new technology which we wanted to avoid. Besides, we also simulated a modified DET flip-flop in Fig.2(b), which use transmission gates to replace all pass transistors in Fig.2(a).…”

“…The first problem is to restructure the flip-flop so as to sample and store the input data at both of its edges. This is precisely a doubleedge-triggered (DET) flip-flop, [3][4][5][6][7] which samples the input data by both the clock's rising edge and falling edge. The second problem is to use the traditional single-edge-triggered (SET) flip-flop (for example, sensitive to clock's falling edge) to compose a new storage system, which can sample the input data on the clock's rising edge as well as its falling edge.…”