ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms

Lü, Kai; Li, Zhaoshi; Liu, Leibo; Wang, Jiawei; Yin, Shouyi; Wei, Shaojun

doi:10.1109/iccad45719.2019.8942089

Cited by 7 publications

(14 citation statements)

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“…1b, the element whose value is 7 is the first element of the third row and its index in the val array is 6. Thus, r_id [3] = 6. Further, to retrieve one element's row index, we need to compare its index in val with the item in r_id .…”

Section: A Sparse Matrix Vector Multiplicationmentioning

confidence: 99%

“…However, this design requires a quite long preprocessing time. In [3], the authors propose a highperformance dataflow engine for CPU-FPGA heterogeneous platform. They utilize the CPU part to fetch nonzero elements' corresponding x's elements sequentially and the FPGA part performs the multiplication and accumulation on the fetched data in parallel.…”

Section: Related Workmentioning

confidence: 99%

“…Since the SpMV is memory-intensive, the bandwidth utilization (BU) is deemed as the performance metric [3]. Matrix preprocessing is a common approach to reduce the memory bandwidth requirement [4].…”

Section: Introductionmentioning

confidence: 99%

“…Only 0.1% to 10% of the peak memory bandwidth can be utilized while executing SpMV on CPUs and GPUs [7]. With high design flexibility and large on-chip memory, FPGAs have been regarded as a promising solution [3] [8] [9]. Among these designs, the dataflow approach [3] achieves a considerable bandwidth utilization in which the execution of SpMV is fully pipelined to overlap the computation latency with the off-chip memory access latency.…”

Section: Introductionmentioning

confidence: 99%

“…With high design flexibility and large on-chip memory, FPGAs have been regarded as a promising solution [3] [8] [9]. Among these designs, the dataflow approach [3] achieves a considerable bandwidth utilization in which the execution of SpMV is fully pipelined to overlap the computation latency with the off-chip memory access latency. However, it didn't take advantage of FPGA's large on-chip memory which leads to non-optimal bandwidth utilization.…”

Section: Introductionmentioning

confidence: 99%

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Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs

Liu

2021

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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Sparse matrix-vector multiplication (SpMV) is of paramount importance in both scientific and engineering applications. The main workload of SpMV is multiplications between randomly distributed nonzero elements in sparse matrices and their corresponding vector elements. Due to irregular data access patterns of vector elements and the limited memory bandwidth, the computational throughput of CPUs and GPUs is lower than the peak performance offered by FPGAs. FPGA's large onchip memory allows the input vector to be buffered on-chip and hence the off-chip memory bandwidth is only utilized to transfer the nonzero elements' values, column indices, and row indices. Multiple nonzero elements are transmitted to FPGA and then their corresponding vector elements are accessed per cycle. However, typical on-chip block RAMs (BRAM) in FPGAs only have two access ports. The mismatch between off-chip memory bandwidth and on-chip memory ports stalls the whole engine, resulting in inefficient utilization of off-chip memory bandwidth. In this work, we reorder the nonzero elements to optimize data reuse for SpMV on FPGAs. The key observation is that since the vector elements can be reused for nonzero elements with the same column index, memory requests of these elements can be omitted by reusing the fetched data. Based on this observation, a novel compressed format is proposed to optimize data reuse by reordering the matrix's nonzero elements. Further, to support the compressed format, we design a scalable hardware accelerator and implement it on the Xilinx UltraScale ZCU106 platform. We evaluate the proposed design with a set of matrices from the University of Florida sparse matrix collection. The experimental results show that the proposed design achieves an average 1.22x performance speedup w.r.t. the state-of-the-art work.

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Section: A Sparse Matrix Vector Multiplicationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%