Recursive Diagonal Torus: an interconnection network for massively parallel computers

Yang, Yue; Amano, Hideharu; Shibamura, Hidetomo; Sueyoshi, Toshinori

doi:10.1109/spdp.1993.395481

Cited by 34 publications

(41 citation statements)

References 13 publications

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“…The RDT structure is constructed by recursively overlaying 2-D diagonal torus [16]. Consider a torus network composed of NxN nodes, where N = nk and both n and k are natural numbers.…”

Section: Structure Of Rdt and Prdtmentioning

confidence: 99%

“…Two routing algorithms for PRDT(2, 1) are implemented in our design: the vector routing [16] and the Johnson coded vector routing [12].…”

Section: Routing Algorithms For Prdtmentioning

confidence: 99%

“…The basic routing algorithm for PRDT (2, 1) is the vector routing algorithm [16], in which a route from a source node to a destination node is represented as a vector. The goal of the vector routing algorithm is to represent the vector with an expression that combines all unit vectors in rank-0 and rank-1 torus and the hop counts.…”

Section: Vector Routing Algorithm (Vr)mentioning

confidence: 99%

“…However, the aforementioned interconnection topologies are either not scalable or not reconfigurable. To address these two problems, a novel class of topologies named Recursive Diagonal Torus (RDT) [16] is proposed for NoCs [17]. The RDT structure is constructed by recursively overlaying 2-D diagonal torus, and it has the following features: recursive structure with constant node degree, smaller diameter and average distance, and embedded mesh/torus topology.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs

Neelkrishnan

Yang

Jiang

et al. 2008

Fifth International Conference on Information Technology: New Generations (Itng 2008)

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This paper presents a parameterized router design which can be applied to build large network-on-chips (NoCs) based on a Perfect Recursive Diagonal Torus (PRDT) IntroductionAs predicted by the International Technology Roadmap for Semiconductors (ITRS) [8], for the next 5 to 10 years, System-on-Chips (SoCs), using 32nm transistors operating below one volt, will grow to multi-billion transistors running at a frequency of 10GHz or higher. One of the major challenges in designing such highly integrated SoCs will be to find an effective way to integrate pre-designed Intellectual Property (IP) cores for power and performance concerns [1]. As the device feature size is continuously shrinking and the bandwidth requirements are increasing, traditional bus-based SoC architectures [1] have been found creating a performance bottleneck. Network-on-Chips (NoCs) thus have emerged as a promising alternative to overcome those limitations of bus-bused architectures by employing a packet-based micro-network for inter-IP communication.In general, a packet-based NoC consists of routers, the network interface between the routers and the IP, and the interconnection network. The major challenges faced by NoC designs include scalability, energy efficiency, and reconfigurability [3]. In designing an NoC system, the interconnection network is the key in addressing these challenges. Numerous interconnection network topologies have been considered for NoCs, including mesh [10], torus [9], fat tree [5], honeycomb [6], and a few others [3]. However, the aforementioned interconnection topologies are either not scalable or not reconfigurable. To address these two problems, a novel class of topologies named Recursive Diagonal Torus (RDT) [16] is proposed for NoCs [17]. The RDT structure is constructed by recursively overlaying 2-D diagonal torus, and it has the following features: recursive structure with constant node degree, smaller diameter and average distance, and embedded mesh/torus topology. A special type of RDT, called Perfect RDT (PRDT) [14] is considered to be a promising on-chip interconnection network topology due to its symmetric structure and simpler link connections than other RDT structures.As the interface of an IP to the on-chip interconnection network, the router design has an important impact to the cost and performance a NoC design. In the literature, a number of NoC router designs have been proposed, such as MANGO router [18], ParIS [2]. However, these routers are tailored for a particular topology and cannot be directly applied to PRDT(2,1)-based NoCs. This paper is focused on developing a parameterized router for PRDT-based NoCs in hardware. As PRDT can be considered as a variation of torus, the router, although designed and optimized for PRDT, is reconfigurable to be applied to build mesh/torus-based NoCs. In specific, the router implements two routing algorithms (vector routing and Johnson coded vector routing), the wormhole switching scheme, the scheduling scheme, buffering strategy, and flow control scheme...

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“…The RDT structure is constructed by recursively overlaying 2-D diagonal torus [16]. Consider a torus network composed of NxN nodes, where N = nk and both n and k are natural numbers.…”

Section: Structure Of Rdt and Prdtmentioning

confidence: 99%

“…Two routing algorithms for PRDT(2, 1) are implemented in our design: the vector routing [16] and the Johnson coded vector routing [12].…”

Section: Routing Algorithms For Prdtmentioning

confidence: 99%

Section: Vector Routing Algorithm (Vr)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs

Neelkrishnan

Yang

Jiang

et al. 2008

Fifth International Conference on Information Technology: New Generations (Itng 2008)

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show abstract

“…It has been previously proved that reducing topological distances by skewing the wrap-around links in rectangular and "L-shape" Tori, results in better system performance (6)(7)(8) . Having lower distances implies higher network throughput and lower packet latencies which reduce the execution times of typical applications running over different kinds of multiprocessor platforms.…”

Section: Motivationmentioning

confidence: 99%

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Martínez

Vallejo

Beivide

et al. 2006

Int J Parallel Prog

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This paper explores the suitability of dense circulant graphs of degree four for the design of on-chip interconnection networks. Networks based on these graphs reduce the Torus diameter in a factor √ 2 which translates into significant performance gains for unicast traffic. In addition, they are clearly superior to Tori when managing collective communications. This paper introduces a new two-dimensional node's labeling of the networks explored which simplifies their analysis and exploitation. In particular, it provides simple and optimal solutions to two important architectural issues: routing and broadcasting. Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.

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Chordal Topologies for Interconnection Networks

Beivide

Martínez

Izu

et al. 2003

Lecture Notes in Computer Science

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Abstract. The class of dense circulant graphs of degree four with optimal distance-related properties is analyzed in this paper. An algebraic study of this class is done. Two geometric characterizations are given, one in the plane and other in the space. Both characterizations facilitate the analysis of their topological properties and corroborate their suitability for implementing interconnection networks for distributed and parallel computers. Also a distance-hereditary non-disjoint decomposition of these graphs into rings is computed. Besides its practical consequences, this decomposition allows us the presentation of these optimal circulant graphs as a particular evolution of the traditional ring topology.

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Recursive Diagonal Torus: an interconnection network for massively parallel computers

Cited by 34 publications

References 13 publications

Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs

Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Chordal Topologies for Interconnection Networks

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