Recovery after hot-carrier injection: Slow versus fast traps

Jong, Maurits J. de; Salm, Cora; Schmitz, Jurriaan

doi:10.1016/j.microrel.2019.06.010

Cited by 7 publications

(3 citation statements)

References 27 publications

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“…The experiments confirm the recently published findings that DAHC recovery shows no gate length dependency [6] and that recovery rates are similar for hydrogen-or deuteriumpassivated transistors [20]. In contrast to earlier work [17], no pronounced difference between the ∆N cp recovery as measured at 100 kHz or 3 MHz. The assumption is that the frequency dependence only emerges when more severe damage is inflicted to the device, in order to produce significant amounts of deep oxide traps [16].…”

Section: A Argonsupporting

confidence: 90%

“…N cp consists of (mainly) shallow interface traps (N it ) and deeper border traps (N ot ). CP-frequencies of f = 100 kHz and f = 3 MHz have been used, since earlier experiments [17] have shown that shallower and deeper traps can be distinguished using these frequencies. Because of the device layout in technologies B and C, CP-measurements could only be done on the devices of technology A.…”

Section: B Measurements and Degradationmentioning

confidence: 99%

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Effect of Ambient on the Recovery of Hot-Carrier Degraded Devices

Jong

Salm

Schmitz

2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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nMOSFETs have been degraded by hot-carrier injection and recovered by annealing in various ambients. Hydrogen will depassivate from the interface due to the hot-carriers, creating dangling bonds, which will cause a shift in the various parameters like the threshold voltage, the subthreshold swing and the interface defect density. This paper investigates how the various ambients (argon, hydrogen, hydrogen plasma and atomic hydrogen) influence the recovery rate of these parameters. Results are discussed in the framework of Stesmans' model for hydrogen passivation at the interface. Furthermore, the influence of a silicon nitride scratch protection layer on the recovery is investigated. These results can be used to enhance the recovery rate and achieve more recovery at a lower anneal temperature, which is important for delaying the accumulative effect of hotcarrier degradation and, as such, extending the device lifetime.

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Section: A Argonsupporting

confidence: 90%

Section: B Measurements and Degradationmentioning

confidence: 99%

Effect of Ambient on the Recovery of Hot-Carrier Degraded Devices

Jong

Salm

Schmitz

2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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“…HCD anneal has been widely studied in the past, using a variety of heat sources. A first possibility is to use a furnace or a heated chuck to reach the anneal temperature [3]- [7]. Secondly, an external microheater can be stacked [8] or monolithically integrated [9] on a chip to induce HCD anneal.…”

Section: Introductionmentioning

confidence: 99%

The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation

Vandemaele

Bury

Tyaginov

et al. 2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans' passivation model for P b -defects in hydrogen gas (H 2 ). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced P b -defects.

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