Recovering and Exploiting Structural Knowledge from CNF Formulas

Ostrowski, Richard; Grégoire, Éric; Mazure, Bertrand; Saïs, Lakhdar

doi:10.1007/3-540-46135-3_13

Cited by 57 publications

(49 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The concept of BCE traces back to [18,Section 2.4] where it was first noted (in dual form, considering formulas in disjunctive normal form) that such clauses can be eliminated without affecting satisfiability. 1 While (partial) elimination of blocked clauses has been proposed before [42], we present in this paper the first systematic analysis of the effectiveness of BCE.…”

Section: Contributionsmentioning

confidence: 99%

See 1 more Smart Citation

Simulating Circuit-Level Simplifications on CNF

2011

View full text Add to dashboard Cite

Boolean satisfiability (SAT) and its extensions have become a core technology in many application domains, such as planning and formal verification, and continue finding various new application domains today. The SAT-based approach divides into three steps: encoding, preprocessing, and search. It is often argued that by encoding arbitrary Boolean formulas in conjunctive normal form (CNF), structural properties of the original problem are not reflected in the CNF. This should result in the fact that CNF-level preprocessing and SAT solver techniques have an inherent disadvantage compared to related techniques applicable on the level of more structural SAT instance representations such as Boolean circuits. Motivated by this, various simplification techniques and intricate CNF encodings for circuit-level SAT instance representations have been proposed. On the other hand, based on the highly efficient CNF-level clause learning SAT solvers, there is also strong support for the claim that CNF is sufficient as an input format for SAT solvers.In this work we study the effect of CNF-level simplification techniques, focusing on SatElite-style variable elimination (VE) and what we call blocked clause elimination (BCE). We show that BCE is surprisingly effective both in theory and in practice on CNF formulas resulting from a standard CNF encoding for circuits: without explicit knowledge of the underlying circuit structure, it achieves the same level of simplification as a combination of circuit-level simplifications and previously suggested polarity-based CNF encodings. We also show that VE can achieve many of the same effects as BCE, but not all. On the other hand, it turns out that VE and BCE are indeed partially orthogonal techniques. We also study 2 the practical effects of combining BCE and VE for reducing the size of formulas and on the running times of state-of-the-art SAT solvers. Furthermore, we address the problem of how to construct original witnesses to satisfiable CNF formulas when applying a combination of BCE and VE.

show abstract

Section: Contributionsmentioning

confidence: 99%

“…Preprocessing techniques have been developed both for circuits and for CNF (for examples of CNF-level simplification techniques, see [37,39,2,42,9,45,19,22,48,32,23]). The way the encoding and simplification/preprocessing is done before the actual solving can have a notable effect on the running times of SAT solvers.…”

Section: Introductionmentioning

confidence: 99%

Simulating Circuit-Level Simplifications on CNF

2011

View full text Add to dashboard Cite

show abstract

“…In the following discussion, we follow the terminology used in [7] and [18]. First, we consider the following CNF formula:…”

Section: Gates and Dependenciesmentioning

confidence: 99%

“…Basically, by finding the sets of clauses corresponding to any of above ones, we can find gates in the CNF (more sophisticated approaches are necessary to detect more gates as described in [7], [8]). An output variable of a gate becomes an input variable of the next gate.…”

Section: Gates and Dependenciesmentioning

confidence: 99%

“…By choosing proper literals, larger problems can be solved efficiently in shorter time. A problem of SAT and MaxSAT is typically given as a propositional conjunctive normal form (CNF), and it is known that the functional dependencies among the clauses (namely, gates in the circuit) can be reconstructed from the given CNF [7], [8], and it helps to solve those problems efficiently [18].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

Kanazawa

Matsumoto

2017

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYWalkSAT (WSAT) is one of the best performing stochastic local search algorithms for the Boolean Satisfiability (SAT) and the Maximum Boolean Satisfiability (MaxSAT). WSAT is very suitable for hardware acceleration because of its high inherent parallelism. Formal verification of digital circuits is one of the most important applications of SAT and MaxSAT. Structural knowledge such as logic gates and their dependencies can be derived from SAT/MaxSAT instances generated from formal verification of digital circuits. Such that knowledge is useful to solve these instances efficiently. In this paper, we first discuss a heuristic to utilize the structural knowledge for solving these problems by using WSAT. Then, we show its implementation on FPGA. The problem size of the formal verification is typically very large, and most data have to be placed in offchip DRAMs. In this situation, the acceleration by FPGA is limited by the throughput and access latency of the DRAMs. In our implementation, data are carefully mapped on the on-chip memory banks and off-chip DRAMs so that most data in the off-chip DRAMs can be continuously accessed using burst-read. Furthermore, a variable-way cache memory comprised of the on-chip memory banks is used in order to hide the DRAM access latency by caching the head portion of the continuous read from the DRAMs and giving them to the circuit till the rest portion is started to be given by the burst-read. We evaluate the performance of our proposed method by changing configuration of the variable-way cache and the processing parallelism, and discuss how much acceleration can be achieved.

show abstract

Bibliography

2009

Constraint Networks

View full text Add to dashboard Cite

Recovering and Exploiting Structural Knowledge from CNF Formulas

Cited by 57 publications

References 11 publications

Simulating Circuit-Level Simplifications on CNF

Simulating Circuit-Level Simplifications on CNF

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

Bibliography

Contact Info

Product

Resources

About