Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

Abstract

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400 o C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.

RRAM for Compute-in-Memory: From Inference to Training

“…We calibrated back-end-of-line (BEOL)-compatible transistors into DNN+NeuroSim to run the M3D benchmark [42]. To be specific, we considered the transistor parameter degradation ratio between the top tier and the bottom substrate of the silicon transistors, as shown in the experimental data for the top tier laser-recrystallized silicon transistors [43]. Furthermore, we also considered the heat dissipation in M3D architecture, by introducing a compact model of the thermal profile [44] into the M3D benchmark framework accounting for (a) top and bottom tiers' power density; (b) the chip area and substrate thickness; and (c) inter-tier BEOL thickness and material.…”

Device and integration technologies for VLSI in post-Moore era

“…CMP 减薄法是在底层器件形成后, 在层间隔离介质上淀积非晶薄膜材料, 通过热处理的方法使该 非晶层再结晶形成上层器件的有源层. 这样形成的薄膜的晶粒尺寸、表面粗糙度与薄膜的原始厚度有 关, 需要用 CMP 进行减薄和表面平坦化, 可以得到 ∼20 nm 厚, 晶粒尺寸 ∼1000 nm, 表面粗糙度低 于 0.5 nm 的类单晶硅膜 [32] . 该方法的优势在于: 通过淀积的方式形成有源层, 工艺复杂度低, 与传统…”