Reconfigured test architecture optimization for TSV-based three-dimensional SoCs

Abstract

The technology of three-dimensional (3D) SoCs is emerging as a promising approach for extending Moore's Law. Managing test architecture design and optimization of 3D integration are crucial challenges. In this paper, we propose a reconfigured test architecture optimization for 3D SoCs, including a novel scheme to minimize the prebond test time and Known-Good Stack (KGS) test to guarantee the yield of 3D SoCs. Experimental results on ITC'02 SoC benchmark circuits show that our scheme reduces the total test time by around 23% on average and nearly 30% in maximum compared with one baseline solution.

An effective structure and flow for pre-bond TSV test

“…These TSV faults may induce the performance degradation, or even result in the function failure of 3D ICs. As a result, it is imperative to detect the TSV faults to assure the quality of 3D ICs [4,5,6,7,8,9,10]. The TSV faults are better to be detected prior to the bonding process.…”