Reconfigurable threshold logic gates with nanoscale DG-MOSFETs

Kaya, Savaş; Hamed, Hesham F. A.; Ting, Darwin T.; Creech, G.L.

doi:10.1016/j.sse.2007.08.011

Cited by 7 publications

(3 citation statements)

References 5 publications

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“…The earlier works and even later ones such as [15], [16], [17], [18], [19], [20], [5], have not been integrated into mainstream VLSI design. It is, however, still is very valuable to develop efficient implementations of threshold functions.…”

Section: A Threshold Logicmentioning

confidence: 99%

A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells

Wagle,

Singh,

Khatri

et al. 2022

Preprint

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In this paper, we describe a design of a mixedsignal circuit for a binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication.

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Section: A Threshold Logicmentioning

confidence: 99%

A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells

Wagle,

Singh,

Khatri

et al. 2022

Preprint

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“…In order to build reconfigurable logic systems, one can also use a threshold logic gates (TLG), which is not as widely known as, but can be more powerful than the elementary Boolean gates studied so far (Kaya et. al, 2007).…”

Section: Dg Threshold Logic Gatesmentioning

confidence: 99%

Advances in Analog Circuits

Tlelo-Cuautle¹

2011

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Esteban Tlelo-Cuautle received a B.Sc. degree from Instituto Tecnológico de Puebla in 1993. He then received both M.Sc. and Ph.D. degrees from Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), in 1995 and 2000, respectively. In 2001 he was appointed as professor-researcher at INAOE. From 2009-2010, he served as a Visiting Researcher in the department of electrical engineering at the University of California Riverside, USA. He has authored four books, ten book chapters, 46 journal articles and around 100 conference papers. He is an IEEE Senior Member, IEICE Member, and a member of the National System for Researchers (SNI-México). He serves in the editorial board of Nonlinear Science Letters B: Chaos, Fractal and Synchronization; Trends in Applied Sciences Research; and Journal of Applied Sciences. He regularly serves as a reviewer in about 22 journals and 15 international conferences.His research interests include systematic synthesis and behavioral modeling and simulation of linear and nonlinear circuits and systems, chaotic oscillators, symbolic analysis, multi-objective evolutionary algorithms, and analog/ RF and mixed-signal design automation tools.

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“…However, the novel DG-MOSFET architecture has not been extensively utilized in the context of TLG circuits, except a prior design that takes advantage of the back gates in a current-mode SR-latch switching [5]. This work presents the first in-depth account of a voltage-mode TLG circuit based on DG-MOSFETs, and further illustrates how this novel CMOS technology can be applied to reconfigurable system design while also improving area and speed performance [1,5].…”

Section: Introductionmentioning

confidence: 99%

Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs

Kaya

Ting

Hamed

2010

Analog Integr Circ Sig Process

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We present a compact and error tolerant implementation of reconfigurable threshold logic gates (TLG) based on nanoscale DG-MOSFET transistors. The use of independently driven double-gate (IDDG) MOSFETs to build a TLG leads not only to fine-grain reconfigurability by way of voltage-adjustable threshold level (T), but also allows one to vary input weights (w i ) or reduce number of inputs (x i ), depending on the design preferences. Operation of the proposed TLG circuits is verified using UFDG SPICE model, and design trade-offs in terms of size, functionality and performance are also indicated. We show that IDDG MOSFETs lead to more efficient and compact TLG circuits that have better design latitude and noise immunity than the conventional counterparts, while also improving the overall reconfigurability. When the backgate dynamic threshold adjustment afforded by the ultrathin (\10 nm) DG-MOSFETs on SOI substrates is properly understood and utilized, similar to the floating-gate logic architectures, it can be effectively harnessed to create reconfigurability beyond T and can simplify TLG circuit design.

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Reconfigurable threshold logic gates with nanoscale DG-MOSFETs

Cited by 7 publications

References 5 publications

A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells

A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells

Advances in Analog Circuits

Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs

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