Reconfigurable systolic architectures for hashing

Panneerselvam, G.; Jullien, G.A.; Bandyopadhyay, Subir; Miller, William C.

doi:10.1109/parbse.1990.77209

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“…The active state list is implemented as a hash table in SRAM with open addressing and collisions resolved by chaining [27]. We store accepted states for the next frame in a separate SRAM and swap the two SRAMs using multiplexers at the end of each frame.…”

Section: B Viterbi Searchmentioning

confidence: 99%

A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models

Price

Glass

Chandrakasan

2015

IEEE J. Solid-State Circuits

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Abstract-We describe an IC that provides a local speech recognition capability for any electronic device. We start with a generic speech decoder architecture that is programmable with industry-standard WFST and GMM speech models. Algorithm and architectural enhancements are incorporated in order to achieve real-time performance amid system-level constraints on internal memory size and external memory bandwidth. A 2.5 × 2.5 mm test chip implementing this architecture was fabricated using a 65 nm process. The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.

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Section: B Viterbi Searchmentioning

confidence: 99%