Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments

Fiethe,; Michalik,; Dierker,; Osterloh,; Zhou, Quan

doi:10.1109/date.2007.364420

Cited by 14 publications

(8 citation statements)

References 5 publications

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“…Based on previous work (e.g. [59,60,61]) it appears realistic to assume the C&DH unit can be realized on two PCBs with a PC/104 form factor, weighing 125 g each and consuming 2.5 W of power in operational and 0.75 W in idle mode.…”

Section: Due To the Intended Use Of Cots Components Radiationmentioning

confidence: 99%

PANIC – A surface science package for the in situ characterization of a near-Earth asteroid

et al. 2011

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This paper presents the results of a mission concept study for an autonomous micro-scale surface lander also referred to as PANIC -the Pico Autonomous Near-Earth Asteroid In Situ Characterizer. The lander is based on the shape of a regular tetrahedron with an edge length of 35 cm, has a total mass of approximately 12 kg and utilizes hopping as a locomotion mechanism in microgravity.PANIC houses four scientific instruments in its proposed baseline configuration which enable the in situ characterization of an asteroid. It is carried by an interplanetary probe to its target and released to the surface after rendezvous. Detailed estimates of all critical subsystem parameters were derived to demonstrate the feasibility of this concept. The study illustrates that a small, simple landing element is a viable alternative to complex traditional lander concepts, adding a significant science return to any near-Earth asteroid (NEA) mission while meeting tight mass budget constraints.

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Section: Due To the Intended Use Of Cots Components Radiationmentioning

confidence: 99%

PANIC – A surface science package for the in situ characterization of a near-Earth asteroid

et al. 2011

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“…Field-Programmable Gate Arrays (FPGAs) are even now used in different application regions, including Space and Flight [1], [2]. Their low cost and remaking limits [3] will Continue making them a Credibility for this kind of missions. Single Event Upsets (SEUs) are basic explanations behind errors in electronic devices, especially in remedial circumstances.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of (72,64) Extended Multibit SEC-DAEC Codes in FPGA

Police¹

2019

IJRASET

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Single error correction and Double-adjacent error correction (SEC-DAEC) codes speaks to a kind of error correction codes (ECCs) equipped for altering single and double-adjacent errors. These codes are important in applications where various adjacent errors may occur, for instance, space. ECC encoders and decoders have an even structure that makes it less demanding to place them into field-programmable gate arrays (FPGAs). This proposes techniques to develop the decoder of SEC-DAEC codes when executed in a FPGA, falling the advantage use when differentiated and the conventionalist use. This paper grows the bits and triple error cure in like manner achieved for that bits nearby SEC-DAEC codes.

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“…This trend will continue growing in a near future due to their re-programmability [12]. As communications are fundamental to spaceborne applications, such as satellites, spacecrafts, unmanned missions, digital filters play an important role in space systems [13].…”

Section: Introductionmentioning

confidence: 99%

Increasing Reliability of FPGA-Based Adaptive Equalizers in the Presence of Single Event Upsets

Liu

Sorrenti²,

Reviriego

et al. 2011

IEEE Trans. Nucl. Sci.

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Reliability is a major concern for electronic circuits, especially for those that operate in harsh environments. One source of problems are Single Event Upsets (SEU), which change the value of flip flops and memory cells. SEUs are a major issue for SRAMbased Field Programmable Gate Arrays (FPGAs), as they may alter the circuit functionality, creating errors that will only be removed if the device is reprogrammed. The cost of traditional techniques to deal with SEUs, like triplication, can be excessive in some applications. One example are Space systems, in which power consumption and weight are limited. In those cases, the use of ad hoc protection techniques that can reduce the cost is interesting. In this paper, new protection techniques for adaptive equalizers implemented in SRAM-based FPGAs are presented. The proposed techniques use the knowledge of the equalizer to provide effective protection at a lower cost. The results show a reduction of up to 70% in the use of resources in comparison to the commercial XTMR solution.Index Terms-Adaptive filters, design cross-section, fault injection, field programmable gate array (FPGA), single event effects.

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Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments

Cited by 14 publications

References 5 publications

PANIC – A surface science package for the in situ characterization of a near-Earth asteroid

PANIC – A surface science package for the in situ characterization of a near-Earth asteroid

Design and Implementation of (72,64) Extended Multibit SEC-DAEC Codes in FPGA

Increasing Reliability of FPGA-Based Adaptive Equalizers in the Presence of Single Event Upsets

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