Reconfigurable pipelined 2-D convolvers for fast digital signal processing

Abstract

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal-and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides highlevel interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated, Dallas, TX. However, the proposed concept is not limited to a particular processor.Index Terms-Architectural tradeoffs, custom computing machine, design methodology, design reuse, DSP function library, hardware/software co-design, reconfigurable hardware accelerator.

Reconfigurable Systems for Cryptography and Multimedia Applications

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Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms

“…Suppose the width of a coefficient kernel is k, then the number of multipliers is k 2 , and the depth of the adder tree is log(k). Multipliers take input from a customised input buffer called line buffer [1], which enables k data read in one clock cycle from the input feature map. The other side of the line buffer connects to a larger input buffer that partly or fully contains the input feature map.…”

“…This design can tackle those three aforementioned challenges: (1) This design is built upon parameterised hardware modules that can be configured for different layer parameters. (2) We develop design models for estimating resource usage of deep CNN architectures.…”

Self-Reconfigurable Constant Multiplier for FPGA

“…1145/2490830 usage and computation speed with respect to conventional blocks [Gustafsson 2007;Xu et al 2008]. However, in some applications, these constants may change in certain time steps, which prevents the use of standard constant multipliers [Bosí et al 1999;Bouganis et al 2009;Huang et al 2008;Shoufan et al 2010]. Some researchers [Chen and Chang 2009;Demirsoy et al 2007;Turner and Woods 2004] have addressed this problem when the constant changes to several predefined values, as it does in FFT, DCT, filters, and many others.…”