Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

Abstract

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

Thermal-aware directional and adaptive routing algorithm for 3D network-on-chip

“…Stacking of dies in three-dimensional integrated circuit (3D-IC) has reduced interconnection delays. 3D network-on-chip (3D NoC) based designs are expected to offer improved performance while using fewer data transfer connections and consuming less power [1], [2]. In conventional NoC architecture, each tile comprises a network interface, processing element (PE), and a router [3], [4].…”