Reconfigurable Data Planes for Scalable Network Virtualization

Abstract

Network virtualization presents a powerful approach to share physical network infrastructure among multiple virtual networks. Recent advances in network virtualization advocate the use of field-programmable gate arrays (FPGAs) as flexible high performance alternatives to conventional host virtualization techniques. However, the limited on-chip logic and memory resources in FPGAs severely restrict the scalability of the virtualization platform and necessitate the implementation of efficient forwarding structures in hardware. The research described in this manuscript explores the implementation of a scalable heterogeneous network virtualization platform which integrates virtual data planes implemented in FPGAs with software data planes created using host virtualization techniques. The system exploits data plane heterogeneity to cater to the dynamic service requirements of virtual networks by migrating networks between software and hardware data planes. We demonstrate data plane migration as an effective technique to limit the impact of traffic on unmodified data planes during FPGA reconfiguration. Our system implements forwarding tables in a shared fashion using inexpensive off-chip memories and supports both Internet Protocol (IP) and non-IP based data planes. Experimental results show that FPGA-based data planes can offer two orders of magnitude better throughput than their software counterparts and FPGA reconfiguration can facilitate data plane customization within 12 seconds. An integrated system that supports up to 15 virtual networks has been validated on the NetFPGA platform.

Reconfigurable Computing Architectures

“…This approach was demonstrated for networking applications for protocol and packet filtering modules in the context of virtual networking [195]. Similarly, entire modules used for SQL database query operations were dynamically configured in milliseconds to enhance application performance [196].…”

Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

“…Depending on the type of matching (i.e., BM versus MM), the complexity of determining the involved UR is substantially different. This determines requirement (2). For the case of BM, each UR maps to exactly one different UV, resulting in |UR| = |UV|.…”

“…Port is the value of the incoming key and is propagated through the tree pipeline. Port ctrl in, meanwhile, holds (1) values key value to be compared against the key at each node, (2) branching information next or urid, and (3) the flag , which tells if a match has been found for the incoming key. In general, any node should be able to store both next node and URID values for the MM case, since multiple matches can occur while traversing the tree.…”

“…Just will be transferred to lookup engine (FPGA) (16) V [ ] ← BV (17) [ ] ← (18) while ≤ and BV ̸ = V [ ] do (8) ← + 1 (9) end while // if BV not found, increment UR counter (10) if ≥ then (11) ← + 1 (12) [ ] ← (13) end if (14) V We note that a subtle issue must be solved for our enhancement to work. In cases (1), (2), and 3 (5) [ ] ← (6) [ ] ← (7) [ ] ← UV. , ER.…”

“…Technology offers several options for implementing packet processing, such as network processors (NPs), custom application-specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs). Among them, FPGAs have been widely adopted for mid-sized and flexible solutions [2]. As resources on these platforms become richer and more efficient as technology evolves, the performance gap with respect to ASICs tends to narrow in time in practical applications due to the higher costs associated to ASIC development.…”