Reconfigurable arithmetic logic unit designed with threshold logic gates

Abstract

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.

Are fungi capacitors?

“…Another potential direction of future studies would be to increase the capacity of the mycelium as a result of modifying the network geometry by varying nutritional conditions and temperature [60,61,62,63], concentration of nutrients [64] or with chemical and physical stimuli [41]. With regards to the impact of our finding for the field of unconventional computing, we believe further research on experimental laboratory implementation of capacitive threshold logic [65,66], adiabatic capacitive logic [67] and capacitive neuromorphic architectures [68] will yield fruitful…”

Capacitive storage in mycelium substrate

“…Another potential direction of future studies would be to increase the capacity of the mycelium as a result of modifying the network geometry by varying nutritional conditions and temperature [14,29,46,47], concentration of nutrients [49] or with chemical and physical stimuli [5]. With regards to the impact of our finding for the field of unconventional computing, we believe further research on experimental laboratory implementation of capacitive threshold logic [43,39], adiabatic capacitive logic [44] and capacitive neuromorphic architectures [61] will yield fruitful insights.…”

High‐speed energy efficient process, voltage and temperature tolerant hybrid multi‐threshold 4:2 compressor design in CNFET technology

“…Equation (16) describes the operation of Sum. Then, (16) and (18) are summarised to (19) considering the threshold. Afterwards the summarised (20) is driven, for Carry with the same ratiocination.…”

“…Afterwards the summarised (20) is driven, for Carry with the same ratiocination. Based on (19) and (20) the Sum and Carry can be generated by using 2 × 1 MUXs in which their select line is (In 1 ⊕ In 2 ⊕ In 3 ), as shown in Fig. 8.…”

“…The usage of the capacitor voltage divider is preferable to avoid high continuous static power dissipation and high‐area wastage [16] Capacitive TLG (CTLG) is an outstanding implementation of threshold logic (TL), in which an array of capacitors easily implements an arithmetic operation of sum‐of‐products [9, 17]. In addition, CTLG benefits from dense, fast and standard CMOS compatible implementation and provides higher fan‐in capacity than that of other solutions such as ganged‐CMOS gate [18] and neuron MOS transistor () [19]. The high integration density is the advantage, while high power consumption, non‐linearity, process dependency and a limited number of fan‐in are its disadvantages [20].…”