Reconfigurable architectures for parallel execution of image processing tasks

Gorgon, Marek Boguslaw

doi:10.2478/s11772-007-0019-3

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Theoretical Foundations For Building Fpga-based Image Proces1

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Cited by 2 publications

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“…The possibility to implement fine−grain parallelization in an FPGA allows for pipelined image processing [6,12,29,38,39]. According to Flynn's classification, this type of multiprocessor architecture is defined as multiple instructions streams single data stream (MISD).…”

Section: Theoretical Foundations For Building Fpga-based Image Procesmentioning

confidence: 99%

Parallel performance of the fine-grain pipeline FPGA image processing system

Gorgon

2012

Opto-Electronics Review

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The use of FPGA circuits in imaging systems increases. They compete with other computing environments. The article describes the indications to be followed while choosing the type of image processing computing system taking under consideration the advantages and disadvantages of each technology: general purpose processor, digital signal processor, graphical processing unit, application specific Integrated circuit and field programmable gate array. Attention is drawn to various video transmission standards. The state of research and development trends in the field of FPGA-based image processing are briefly presented. A defining processing performance method for image processing is proposed. It is proven that for a pipeline architecture implemented in FPGA, a linear speedup is achieved and parallel efficiency is equal to one.

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Section: Theoretical Foundations For Building Fpga-based Image Procesmentioning

confidence: 99%