Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA

Abstract

The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. We have to propose and compare three levels of Galois Field GF(2 163 ), GF(2 193 ), and GF(2 256 ). The proposed architecture is based on Lopez-Dahab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for GF(2 163 ) field arithmetic. The proposed GF(2 193 ) is based on an efficient Montgomery add and double algorithm, also the Karatsuba-Ofman multiplier and Itoh-Tsujii algorithm are used as the inverse component. The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer. The another proposed architecture GF(2 256 ) is based on applications for which compactness is more important than speed. The FPGA's dedicated multipliers and carry-chain logic are used to obtain the small data path. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption. Finally, we have to implement our design using Xilinx XC4VLX200 FPGA device.

Implementation of ECC on FPGA using Scalable Architecture with equal Data and Key for WSN

“…So groups and f nite f elds are two vital concepts required for the Elliptic Curve Cryptographic implementation. 16-bit microcontrollers that consume low power but have restricted memory resources and low processing capabilities. The probability of communication failures in nodes are more in WSNs, than traditional networks as nodes are often located in unattended places and they use a limited power supply.…”

“…ECC using normal basis representation over GF (2 m ) is implemented in this work. Rahuman et al, [15] [16]propose an architecture with Lopez-Dahab Elliptic Curve Point Multiplication algorithm that is based on an eff cient Montgomery add and double algorithm using Xilinx XCSVLX200 FPGA device. GF (2 193 ) with Gaussian normal basis for f eld arithmetic, KaratsubaOfman multiplier and Itoh-Tsujii algorithm are used as the inverse component.…”

“…In [10]- [13] Elliptic Curve Scalar Multiplication architectures are implemented using different multipliers. In [16], the design is implemented on Xilinx XC4VLX200 device. In this FPGA 16.209 slices are utilized, which shows more hardware usage compared to our design.…”