Reconfigurable architecture for elementary functions evaluation

Abstract

A reconfigurable architecture for efficient computation of several elementary functions, in double precision floating-point format, is presented in this paper. The main idea is to tailor the computation method towards FPGA resources of Virtex-II circuits to increase the execution performances of these functions. Our method employs a piecewise Minimax approximation and look-up tables. To attain a precision of one ULP (Unit in Last Place) without exceeding the memory available in Virtex-II FPGAs, third degree approximation polynomials were needed which have been evaluated using Horner's scheme to reduce the multiplications number. Some strategies were used in the Fused Multiplier Adder (FMAs) to overcome the carry propagation such as the carry save representation for the intermediate results to minimize the multipliers delay.A pipelined architecture implementing our method is proposed and its execution time and area costs estimations are presented showing that the architecture has attained a cycle time of 17.372 ns and an operating frequency of 57 MHz with a latency of four cycles and a throughput of one result per cycle.

Efficient polynomial evaluation algorithm and implementation on FPGA

“…Many designs with polynomial evaluation have been implemented in FPGA [17,22,23] and naturally, various methods have been proposed to speed up polynomial evaluation methods in FPGAs [16,20,21,[24][25][26].…”

“…On the other hand, if designs have to be approximated across the whole range, sub-intervals could be divided. Although more memory might be needed for breaking down into segmented ranges, it could significantly reduce the degree required for the same precision [26]. Figure 2.4 shows the function before and after range reduction optimization and Figure 2.5 illustrats how the subintervals are formed.…”