Reconfigurable adders for Binary/BCD addition/subtraction

Ahmed, Syed Ershad; Veeramanchaneni, Sreehari; Muthukrishnan, N. Moorthy; Srinivas, M.B.

doi:10.1109/primeasia.2011.6075082

Cited by 2 publications

(9 citation statements)

References 7 publications

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“…Creating and employing the adder used in [6] and this study is centered on the structure of Sklansky [7] adder.…”

Section: B the Suggested Circuit Functioning In Decimal Casementioning

confidence: 99%

“…For both cases of X>Y and , subtraction is tested. The situation here is the transference of the carry from one level to another, if >y, the subtraction is binary (Subtraction = X+(-Y) where -Y is Y NEW), and at the start 1's complement determines Y, and as declared in [6], the subtraction is done. View the procedure in the example below.…”

Section: B the Suggested Circuit Functioning In Decimal Casementioning

confidence: 99%

“…The recommended architecture contains different parts such as: pre-correct X and Y "the impression of pre-correct is taken from [6]," post-correct and adder, and restructuring. All design parts are analyzed later.…”

Section: The Recommended Architectural Designmentioning

confidence: 99%

“…Different high-speed adders like CARRY LOOK AHEAD and CARRY SAVE ADDER are used in BCD of [3]- [5] in order to make their circuit work more properly, while in [6] another type of adder is used with a new ability of restructuring and with this, the adder is capable of adding and subtracting BCD practically. In this paper the sign bit of BCD numbers are considered without any importance, and in [6], the restructuring ability is used which causes an output signal called EOP, which only works at the end of the operation.…”

Section: Introductionmentioning

confidence: 99%

“…This paper has tried to clarify the final computation by using the ability of restructuring for BCD/binary and without considering any sign for adding/subtraction. The paper has also discussed the design in [6] and the problems about it below.…”

Section: Introductionmentioning

confidence: 99%

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Design of Addition/Subtraction for BIN/BCD Numbers

Tavakoli¹,

internationaluniversity²,

Parvin³

et al. 2017

IJET

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This paper aims to find a solution for a new design of binary / BCD adder / subtraction to increase the speed of operations and decrease the delays in signed numbers as well as the unsigned ones. A very important operation in mathematics for digital systems is adding binary/BCD numbers. Many different ways have been presented for addition and subtraction of BCD,this paper has presents no signbit numbers adder and subtractor many papers presented adder and subtractor for binary BCD numbers but all of them have some problems with their final assessment in this paper this problem is solved by adding EOP (end of operation signal). Here, a new design for addition or subtraction has been offered, without taking the signbit in BCD format that works perfectly.

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“…Creating and employing the adder used in [6] and this study is centered on the structure of Sklansky [7] adder.…”

Section: B the Suggested Circuit Functioning In Decimal Casementioning

confidence: 99%

Section: B the Suggested Circuit Functioning In Decimal Casementioning

confidence: 99%

Section: The Recommended Architectural Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of Addition/Subtraction for BIN/BCD Numbers

Tavakoli¹,

internationaluniversity²,

Parvin³

et al. 2017

IJET

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A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Allwin¹,

Chen²

2021

JCC

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Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm 2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

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Reconfigurable adders for Binary/BCD addition/subtraction

Cited by 2 publications

References 7 publications

Design of Addition/Subtraction for BIN/BCD Numbers

Design of Addition/Subtraction for BIN/BCD Numbers

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

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