Reconfigurable Acceleration of Short Read Mapping

Arram, James; Tsoi, Kuen Hung; Luk, Wayne; Jiang, Peiyong

doi:10.1109/fccm.2013.57

Cited by 32 publications

(27 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In the case of BWA-MEM, this is impractical as the inexact mapping calls are dynamically generated for alignments of varying length, which makes the batching strategy inefficient due to the large communication and temporary data overheads this would require. Although many accelerated Seed-and-Extend based mapping tools have been proposed (for example [13]), results from these implementations are not directly comparable. In bioinformatics, exactness of results is critical, as larger population studies can take several years to complete and intermediate results need to be comparable.…”

Section: Related Workmentioning

confidence: 99%

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

Houtgast

Sima²,

Marchiori³

et al. 2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

Abstract-Next Generation Sequencing techniques have dramatically reduced the cost of sequencing genetic material, resulting in huge amounts of data being sequenced. The processing of this data poses huge challenges, both from a performance perspective, as well as from a power-efficiency perspective. Heterogeneous computing can help on both fronts, by enabling more performant and more power-efficient solutions.In this paper, power-efficiency of the BWA-MEM algorithm, a popular tool for genomic data mapping, is studied on two heterogeneous architectures. The performance and powerefficiency of an FPGA-based implementation using a single Xilinx Virtex-7 FPGA on the Alpha Data add-in card is compared to a GPU-based implementation using an NVIDIA GeForce GTX 970 and against the software-only baseline system. By offloading the Seed Extension phase on an accelerator, both implementations are able to achieve a two-fold speedup in overall application-level performance over the software-only implementation. Moreover, the highly customizable nature of the FPGA results in much higher power-efficiency, as the FPGA power consumption is less than one fourth of that of the GPU. To facilitate platform and tool-agnostic comparisons, the base pairs per Joule unit is introduced as a measure of power-efficiency. The FPGA design is able to map up to 44 thousand base pairs per Joule, a 2.1x gain in power-efficiency as compared to the software-only baseline.

show abstract

Section: Related Workmentioning

confidence: 99%

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

Houtgast

Sima²,

Marchiori³

et al. 2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

show abstract

“…A significant number of papers have been published that either use FPGAs (see, e.g., [1], [9], [24], [25], [25], [26], [27], [28], [29], [30], [31]) or GPUs (see, e.g., [32], [33]). For instance in [24], the authors propose a hybrid system for short read mapping utilizing both FPGA-based hardware and CPU-based software: the hardware implements parallel block-wise alignment structure to approximate the conventional dynamic programming algorithm.…”

Section: Related Workmentioning

confidence: 99%

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

Fernandez

Villarreal

Lonardi

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

View full text Add to dashboard Cite

Abstract-While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., BOWTIE, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for BOWTIE that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHASTrunning on the Convey HC-1 achieved up to 70x speedup compared to BOWTIE (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to BOWTIE running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for BOWTIE, so it can be incorporated in any analysis pipeline that uses BOWTIE (e.g., TOPHAT).

show abstract

“…In [89] and [72], Arram et al introduce a hardware design that incorporates specialized matchers for exact and approximate sequence alignment, while at the same time runtime reconfiguration is used to fully populate the FPGA with each type of matchers. Such decoupling enables the flexibility of optimizing each matcher according to the intended workload, hence resulting in higher parallelism and performance.…”

Section: Mappingmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

Abstract-Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPUdays to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming flexibility and thus has not been commensurately used by practitioners. Therefore, this paper aims to provide a thorough survey of the proposed accelerators by giving a qualitative categorization based on their algorithms and speedup. A comprehensive comparison between work is also presented so as to guide selection for biologist, and to provide insight on future research direction for FPGA scientists.

show abstract

Reconfigurable Acceleration of Short Read Mapping

Cited by 32 publications

References 15 publications

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Contact Info

Product

Resources

About