Reconfigurable acceleration of fitness evaluation in trading strategies

Funie, Andreea Ingrid; Grigoras, Paul; Burovskiy, Pavel; Luk, Wayne; Salmon, Mark

doi:10.1109/asap.2015.7245736

Cited by 4 publications

(4 citation statements)

References 15 publications

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“…Three architecture types are supported: static, partial-reconfiguration and full-reconfiguration. Our approach offers alternative solutions when a static design becomes too large because of too many different trading strategies or the trading strategies themselves are very complex and occupy a significant amount of resources [8]. If the resources of a given device run out, a larger FPGA would be needed, but if not available, our framework offers the user a low-cost, resource and performance efficient solution.…”

Section: Discussionmentioning

confidence: 99%

Custom Framework for Run-Time Trading Strategies

Funie

Guo

Niu

et al. 2017

Lecture Notes in Computer Science

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Abstract. A trading strategy is generally optimised for a given market regime. If it takes too long to switch from one trading strategy to another, then a sub-optimal trading strategy may be adopted. This paper proposes the first FPGA-based framework which supports multiple trend-following trading strategies to obtain accurate market characterisation for various financial market regimes. The framework contains a trading strategy kernel library covering a number of well-known trend-following strategies, such as "triple moving average". Three types of design are targeted: a static reconfiguration trading strategy (SRTS), a full reconfiguration trading strategy (FRTS), and a partial reconfiguration trading strategy (PRTS). Our approach is evaluated using both synthetic and historical market data. Compared to a fully optimised CPU implementation, the SRTS design achieves 11 times speedup, the FRTS design achieves 2 times speedup, while the PRTS design achieves 7 times speedup. The FRTS and PRTS designs also reduce the amount of resources used on chip by 29% and 15% respectively, when compared to the SRTS design.

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Section: Discussionmentioning

confidence: 99%

Custom Framework for Run-Time Trading Strategies

Funie

Guo

Niu

et al. 2017

Lecture Notes in Computer Science

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“…The above considerations move us to implement the fitness functions in hardware to enhance the system performance. These functions have been accelerated by means of FPGA devices in genetic programs for financial markets [ 25 ], spatial image filters [ 26 ], filtered image signals [ 27 ], test cases [ 28 ], and many other engineering applications.…”

Section: Introductionmentioning

confidence: 99%

Fine-grained parallelization of fitness functions in bioinformatics optimization problems: gene selection for cancer classification and biclustering of gene expression data

et al. 2016

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BackgroundMetaheuristics are widely used to solve large combinatorial optimization problems in bioinformatics because of the huge set of possible solutions. Two representative problems are gene selection for cancer classification and biclustering of gene expression data. In most cases, these metaheuristics, as well as other non-linear techniques, apply a fitness function to each possible solution with a size-limited population, and that step involves higher latencies than other parts of the algorithms, which is the reason why the execution time of the applications will mainly depend on the execution time of the fitness function. In addition, it is usual to find floating-point arithmetic formulations for the fitness functions. This way, a careful parallelization of these functions using the reconfigurable hardware technology will accelerate the computation, specially if they are applied in parallel to several solutions of the population.ResultsA fine-grained parallelization of two floating-point fitness functions of different complexities and features involved in biclustering of gene expression data and gene selection for cancer classification allowed for obtaining higher speedups and power-reduced computation with regard to usual microprocessors.ConclusionsThe results show better performances using reconfigurable hardware technology instead of usual microprocessors, in computing time and power consumption terms, not only because of the parallelization of the arithmetic operations, but also thanks to the concurrent fitness evaluation for several individuals of the population in the metaheuristic. This is a good basis for building accelerated and low-energy solutions for intensive computing scenarios.Electronic supplementary materialThe online version of this article (doi:10.1186/s12859-016-1200-9) contains supplementary material, which is available to authorized users.

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“…Depending on the total runtime, the impact of run-time reconfiguration may be significant. For example in [10], evaluating 992 expressions on 3.84M data points will take approximately 12 seconds for a fully accelerated version.…”

Section: Challengesmentioning

confidence: 99%

“…There has been great interest in applying reconfigurable solutions to genetic programming [5][6][7][8][9][10][11][12][13][14][15][16][17][18] and substantial progress has been achieved, however, there are still important limitations which restrict the applicability of these solutions in real environments and that we propose to address in our work such as: high latency due to fitness evaluation, simple trading strategies due to GPs represented with reduced complexity s.a. bit-strings instead of trees, small number of individuals evaluated, small number of iterations to reach the maturity of a GP population.…”

Section: Introductionmentioning

confidence: 99%

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

Funie

Grigoras

Burovskiy

et al. 2017

J Sign Process Syst

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Genetic programming can be used to identify complex patterns in financial markets which may lead to more advanced trading strategies. However, the computationally intensive nature of genetic programming makes it difficult to apply to real world problems, particularly in realtime constrained scenarios. In this work we propose the use of Field Programmable Gate Array technology to accelerate the fitness evaluation step, one of the most computationally demanding operations in genetic programming. We propose to develop a fully-pipelined, mixed precision design using run-time reconfiguration to accelerate fitness evaluation. We show that run-time reconfiguration can reduce resource consumption by a factor of 2 compared to previous solutions on certain configurations. The proposed design is up to 22 times faster than an optimised, multithreaded software implementation while achieving comparable financial returns.

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Reconfigurable acceleration of fitness evaluation in trading strategies

Cited by 4 publications

References 15 publications

Custom Framework for Run-Time Trading Strategies

Custom Framework for Run-Time Trading Strategies

Fine-grained parallelization of fitness functions in bioinformatics optimization problems: gene selection for cancer classification and biclustering of gene expression data

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

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