Recon.gurable Computing and Digital Signal Processing

Tessier, Russell; Burleson, Wayne

doi:10.1201/9780203908068.ch4

Cited by 48 publications

(46 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The main advantage to digital signal processing within an FPGA is the ability to adapt the implementation to match system requirements [2,3]. This means in a multiple-channel or high-speed system, you can take advantage of the parallelism within the device to maximize performance.…”

Section: Iifpga For Dspmentioning

confidence: 99%

Comparative Analysis and Efficient VLSI Implementation of FIR Filter

Kadam¹,

SAWARKAR²,

Mande³

2014

IJAREEIE

View full text Add to dashboard Cite

ABSTRACT:In this paper, we present suitable design optimization for area-delay efficient implementation of finite impulse response (FIR) filter on Field Programmable Gate Array (FPGA). Architectural optimization done in MATLAB/Simulink environment, Hardware description language (HDL) netlist produced by System Generator enables emulation on FPGA and also serves as design entry for chip realization. The design of digital filter characterized by minimum critical path and latency, low cost and reduced complexity. Considering above parameters different architectures are implemented such as transpose-form, pipelined filter and parallel processing. Result shows comparison for maximum frequency, resource utilization and reduced latency.

show abstract

Section: Iifpga For Dspmentioning

confidence: 99%

Comparative Analysis and Efficient VLSI Implementation of FIR Filter

Kadam¹,

SAWARKAR²,

Mande³

2014

IJAREEIE

View full text Add to dashboard Cite

show abstract

“…Configurable or adaptive computing capitalizes on the static and/or run time reconfiguration of FPGA-like or switching devices and has been an active research and experimentation area ever since the introduction of commercial FPGAs [7][8][9][10][11][12][13][14][17][18][19][20]. By loading various system configurations into FPGAs (often on the fly) as needed, the designer can achieve greater hardware functionality with the same hardware.…”

Section: Configurable Computing: An Overviewmentioning

confidence: 99%

Parallel LU factorization of sparse matrices on FPGA‐based configurable computing engines

Wang

Ziavras

2004

Concurrency and Computation

View full text Add to dashboard Cite

Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation-intensive applications. With steady advances in silicon technology, as predicted by Moore's Law, FieldProgrammable Gate Array (FPGA) technologies have enabled the implementation of System-On-a-Programmable-Chip (SOPC or SOC) computing platforms, which, in turn, have given a significant boost to the field of configurable computing. It is possible to implement various specialized parallel machines in a single silicon chip. In this paper, we describe our design and implementation of a parallel machine on an SOPC development board, using multiple instances of a soft IP configurable processor; we use this machine for LU factorization. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our approach.

show abstract

“…FPGAs are hardware devices whose functions are not fixed and can be programmed in-system. It provides an attractive solution to developers needing custom logic for short time-to-market products [10,11]. It has got high acceptance as a promising alternative for the implementation of block ciphers.…”

mentioning

confidence: 99%

A Comparative Analysis of Pipelined and Area Optimized Blowfish Algorithm in FPGA for embedded tiny Sensor Node

Chatterjee¹,

M²

2017

IJET

View full text Add to dashboard Cite

Abstract-With the unprecedented growth of modern technology the need for protecting data has increased vehemently in wireless sensor network. This need is not only restricted to the military but also subsumes daily lives as well. Hence safeguarding of data in wireless sensor network is one of the leading fields of research in modern times. Area has been a major stumbling block faced while designing encryption algorithms on hardware for sensor network as it involves tiny sensor nodes. The Blowfish algorithm is one of the fastest block ciphers and may be an efficient alternative to the existing encryption algorithms like AES, DES, IDEA etc. In this paper, pipelined hardware architecture (for enhancement of the speed) and area-optimized hardware architecture (for minimization of the size) are both designed for Blowfish algorithm and a comparative performance analysis has been made to trade off between the space and time complexities for embedded tiny sensor node. The architectures were implemented by verilog which were synthesized, placed and routed in Spartan3e chip XC3s500e-5fg320 using ISE Design Suite 12. , a CRSN consists of tiny low power sensor nodes embedded into mobile phones that adapts to the changing environment of the existing cellular network by analyzing the RF surroundings and adjusting the spectrum use appropriately to send sensory data of explosive traces within a defined territory to the respective service provider, which in turn would inform the law and enforcement agency or Police to combat terrorism. The hardware implementation of any encryption scheme for this type of application requires crucial analysis between time and space complexity of the chosen algorithm for the additional embedded hardware and computational overhead which in turn affects the speed and size of respectively of the embedded tiny sensor nodes [4,5]. Smaller the size and higher the speed better is the performance with regard to portability and throughput respectively. The idea is to design hardware architecture for an encryption algorithm and analyze its space and time complexities. Several symmetric key algorithms are designed, among which DES, Triple DES, AES, Blowfish are widely used. Bruce Schneier designed blowfish in 1993 as a fast, free alternative to existing encryption algorithms [6,7]. Since then this algorithm has been used considerably, and it is slowly gaining acceptance as a strong encryption algorithm. The Blowfish algorithm based on Feistel Network consists of 64 bit input data where same algorithmic operations are performed in each iteration round, except last round and has many advantages. The iteration rounds are suitable and efficient for hardware implementation using simple operations like exclusive-OR and addition on 32 bit word. The relative strength of an encryption algorithm depends on the key length. Blowfish uses variable length (32-448 bits) key and it is less complex and provides higher speed as compared to other existing algorithms [8,9]. So it is suitable for CRSN applications which exchange...

show abstract

Recon.gurable Computing and Digital Signal Processing

Cited by 48 publications

References 0 publications

Comparative Analysis and Efficient VLSI Implementation of FIR Filter

Comparative Analysis and Efficient VLSI Implementation of FIR Filter

Parallel LU factorization of sparse matrices on FPGA‐based configurable computing engines

A Comparative Analysis of Pipelined and Area Optimized Blowfish Algorithm in FPGA for embedded tiny Sensor Node

Contact Info

Product

Resources

About