Recent trends in software and hardware for GPGPU computing: A comprehensive survey

Neelima, B.; Raghavendra, Prakash S.

doi:10.1109/iciinfs.2010.5578685

Cited by 12 publications

(5 citation statements)

References 6 publications

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“…Each core can preserve number of thread contexts, specific to the architecture. CUDA has zero-overhead scheduling, that is maintained by tolerating the data fetch latency by switching between the threads ( [20], [21]). …”

Section: A Gpu Architecturementioning

confidence: 99%

A GPU Framework for Sparse Matrix Vector Multiplication

Neelima

Reddy

Raghavendra

2014

2014 IEEE 13th International Symposium on Parallel and Distributed Computing

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The hardware and software evolutions related to Graphics Processing Units (GPUs), for general purpose computations, have changed the way the parallel programming issues are addressed. Many applications are being ported onto GPU for achieving performance gain. The GPU execution time is continuously optimized by the GPU programmers while optimizing pre-GPU computation overheads attracted the research community in the recent past. While GPU executes the programs given by a CPU, pre-GPU computation overheads does exists and should be optimized for a better usage of GPUs. The GPU framework proposed in this paper improves the overall performance of the application by optimizing pre-GPU computation overheads along with GPU execution time. This paper proposes a sparse matrix format prediction tool to predict an optimal sparse matrix format to be used for a given input matrix by analyzing the input sparse matrix and considering pre-GPU computation overheads. The sparse matrix format predicted by the proposed method is compared against the best performing sparse matrix formats posted in the literature. The proposed model is based on the static data that is available from the input directly and hence the prediction overhead is very small. Compared to GPU specific sparse format prediction, the proposed model is more inclusive and precious in terms of increasing overall application's performance.

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Section: A Gpu Architecturementioning

confidence: 99%

A GPU Framework for Sparse Matrix Vector Multiplication

Neelima

Reddy

Raghavendra

2014

2014 IEEE 13th International Symposium on Parallel and Distributed Computing

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“…The memory requests from a warp to a shared memory can also create a bank conflict, which also increases the number of clock cycles required for the memory access of a warp. GPU hides the latency of one warp with a computation of another warp to overcome the memory access delays .…”

Section: Gpu Architecture and Cuda Programming Modelmentioning

confidence: 99%

“…GPU hides the latency of one warp with a computation of another warp to overcome the memory access delays [5]. A warp cannot be launched until all the memory requests in that warp are executed.…”

Section: Introductionmentioning

confidence: 99%

Communication and computation optimization of concurrent kernels using kernel coalesce on a GPU

Neelima

Reddy

Raghavendra

2013

Concurrency and Computation

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General purpose computation on graphics processing unit (GPU) is rapidly entering into various scientific and engineering fields. Many applications are being ported onto GPUs for better performance. Various optimizations, frameworks, and tools are being developed for effective programming of GPU. As part of communication and computation optimizations for GPUs, this paper proposes and implements an optimization method called as kernel coalesce that further enhances GPU performance and also optimizes CPU to GPU communication time. With kernel coalesce methods, proposed in this paper, the kernel launch overheads are reduced by coalescing the concurrent kernels and data transfers are reduced incase of intermediate data generated and used among kernels. Computation optimization on a device (GPU) is performed by optimizing the number of blocks and threads launched by tuning it to the architecture. Block level kernel coalesce method resulted in prominent performance improvement on a device without the support for concurrent kernels. Thread level kernel coalesce method is better than block level kernel coalesce method when the design of a grid structure (i.e., number of blocks and threads) is not optimal to the device architecture that leads to underutilization of the device resources. Both the methods perform similar when the number of threads per block is approximately the same in different kernels, and the total number of threads across blocks fills the streaming multiprocessor (SM) capacity of the device. Thread multi-clock cycle coalesce method can be chosen if the programmer wants to coalesce more than two concurrent kernels that together or individually exceed the thread capacity of the device. If the kernels have light weight thread computations, multi clock cycle kernel coalesce method gives better performance than thread and block level kernel coalesce methods. If the kernels to be coalesced are a combination of compute intensive and memory intensive kernels, warp interleaving gives higher device occupancy and improves the performance. Multi clock cycle kernel coalesce method for micro-benchmark1 considered in this paper resulted in 10-40% and 80-92% improvement compared with separate kernel launch, without and with shared input and intermediate data among the kernels, respectively, on a Fermi architecture device, that is, GTX 470. A nearest neighbor (NN) kernel from Rodinia benchmark is coalesced to itself using thread level kernel coalesce method and warp interleaving giving 131.9% and 152.3% improvement compared with separate kernel launch and 39.5% and 36.8% improvement compared with block level kernel coalesce method, respectively. 48 B. NEELIMA, G. R. M. REDDY AND P. S. RAGHAVENDRA models such as compute unified device architecture (CUDA), Open specification for Compute Language. The data parallel applications are ported onto GPU, and GPU can give higher performances than CPU for such applications. The resource allocation on GPU is defined at the grid level by the programmer. The programs have usually a g...

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“…With the advent of GPGPU, it is now possible to exploit the massive computing capability of a GPU by the use of API making it easily programmable. One such programming API that has been introduced by NVIDIA for parallel computing using GPU is the compute unified device architecture (CUDA) . CUDA enables programmers to write a sequence of code that can implicitly run on the GPU for better performance.…”

Section: Introductionmentioning

confidence: 99%

Kepler GPU accelerated recursive sorting using dynamic parallelism

Neelima¹,

Shamsundar²,

Narayan

et al. 2016

Concurrency and Computation

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Summary This paper focuses on the performance gain obtained on the Kepler graphics processing units (GPUs) for multi‐key quicksort. Because multi‐key quicksort is a recursive‐based algorithm, many of the researchers have found it tedious to parallelize the algorithm on the multi and many core architectures. A survey of the state‐of‐the‐art string sorting algorithms and a robust insight of the Kepler GPU architecture gave rise to an intriguing research idea of matching the template of multi‐key quicksort with the dynamic parallelism feature offered by the Kepler‐based GPU's. The CPU parallel implementation has an improvement of 33 to 50% and 62 to 75 improvement when compared with 8‐bit and 16‐bit parallel most significant digit radix sort, respectively. The GPU implementation of multi‐key quicksort gives 6× to 18× speed up compared with the CPU parallel implementation of parallel multi‐key quicksort. The GPU implementation of multi‐key quicksort achieves 1.5× to 3× speed up when compared with the GPU implementation of string sorting algorithm using singleton elements in the literature. Copyright © 2016 John Wiley & Sons, Ltd.

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Recent trends in software and hardware for GPGPU computing: A comprehensive survey

Cited by 12 publications

References 6 publications

A GPU Framework for Sparse Matrix Vector Multiplication

A GPU Framework for Sparse Matrix Vector Multiplication

Communication and computation optimization of concurrent kernels using kernel coalesce on a GPU

Kepler GPU accelerated recursive sorting using dynamic parallelism

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