Recent advances in understanding the bias temperature instability

Grasser, T.; Kaczer, B.; Goes, Wolfgang; Reisinger, H.; Aichinger, Thomas; Hehenberger, Ph.; Wagner, P.-J.; Schanovsky, F.; Franco, J.; Roussel, Ph.; Nelhiebel, Michael

doi:10.1109/iedm.2010.5703295

Cited by 99 publications

(61 citation statements)

References 5 publications

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“…We study the duty-factor and frequency dependence in the light of the recently proposed capture/emission time (CET) map model [7,[21][22][23] and demonstrate that the recoverable component of BTI can only to the first-order be captured by a two-state defect model. By using a three-state defect model, consistent with detailed studies on the microscopic defect properties [24,25], the experimentally observed frequency dependence can be reproduced for a wide range of technologies.…”

Section: Introductionmentioning

confidence: 61%

On the frequency dependence of the bias temperature instability

Kaczer

Reisinger

Wagner

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-An accurate understanding of the duty-factor and frequency dependence of the bias temperature instability (BTI) is essential since it can transfer to significant lifetime benefits. Contradictory reports regarding the frequency dependence have been published in literature, with particularly older studies and those interpreted in the framework of the reaction-diffusion model claiming BTI to be frequency-independent. Newer studies, on the other hand, clearly show a frequency-dependent component of BTI. Here we discuss this frequency dependence using the recently suggested capture/emission time map model, which explains BTI as a collection of a large number of independent first-order reactions of defects with two states. While this model can explain most features observed in DC and low-frequency AC stress experiments, it does not fully capture the experimentally observed frequency and duty-factor dependence. However, when a more accurate defect model is considered, which describes charging of the defect via an intermediate state, good accuracy with experimental data is obtained.

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Section: Introductionmentioning

confidence: 61%

On the frequency dependence of the bias temperature instability

Kaczer

Reisinger

Wagner

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…8; for a path consisting of cells with independent variations, the overall variance goes down by 1/√ , according to central limit theorem (CLT) 2 . Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Moreover, the charge trapping model explains the observation that for small-area devices the degradation and recovery of Δ proceed in discrete steps [2], which is similar to the case of random telegraph noise (RTN) and 1/f 2 noise. Based on the charge trapping model, the intrinsic variability of BTI effect was explored analytically in [3], which indicates the possibility of very large device-level variations for smallgeometry FETs, leading to orders-of-magnitude lifetime variations.…”

Section: Introductionmentioning

confidence: 89%

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Understanding the impact of transistor-level BTI variability

Fang

Sapatnekar

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-Recent work has shown large variations due to biastemperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.

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“…The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist.…”

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confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

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Recent advances in understanding the bias temperature instability

Cited by 99 publications

References 5 publications

On the frequency dependence of the bias temperature instability

On the frequency dependence of the bias temperature instability

Understanding the impact of transistor-level BTI variability

What happens when circuits grow old: Aging issues in CMOS design

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