Recent advances in processing and characterization of edgeless detectors

Abstract

During past five years VTT has actively developed edgeless detector fabrication process. The straightforward and high yield process relies on ion-implantation to activate the edges of the detector. A recent fabrication process was performed at VTT to provide p-on-n edgeless detectors. The layout contained DC-and AC-coupled strip detector and pixel detectors for Medipix/Timepix readouts. The fabricated detector thicknesses were 50, 100 and 150 µm. Electrical characterization was done for 5×5 mm 2 edgeless diodes on wafer level. All measured electrical parameters showed a dramatic dependence on the diode thickness. Leakage current was measured below 10 nA/cm 2 at full depletion. Calculation using a theoretical approximation indicates the diode surface generation current of less than 300 pA. The breakdown voltages were measured to be above 140 V and increased as a function of diode thickness. Reverse bias of 10 V is enough to fully deplete designed edgeless diodes. Leakage current dependence of temperature was investigated for both p-on-n and previous n-on-n edgeless detectors and results show that the leakage current doubles for every 8.5 degree Celsius rise in temperature. TCAD device simulations reveal that breakdown occurs at the lateral p-n junction where the electric field reaches its highest value. Thick edgeless diodes have wider bulk space that allows electric potential to drop and causes smaller curvature of the equipotential lines. This releases the accumulation of electric field at the corner of anode and increases the breakdown voltage. A good match of the simulated and the measured capacitance-voltage curves enables identification of proper parameters used in the simulation.

Silicon technologies for the CLIC vertex detector

“…The active edge technology [11] is an interesting option to reduce the amount of passive sensor area and thus the overall material budget of the detector. For this, the backside implant is extended to the edge of the sensor.…”

Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

“…Trenches are realized around the perimeter of each sensor with Deep Reactive Ion Etching (DRIE) using the mechanical support offered by the handle wafer of the SOI stack. A boron implantation is performed in the trenches with a four-quadrant ion implantation [10], allowing to extend the depleted volume up to the edges. After the UBM processing, the handle wafer is removed, singularizing the structures.…”

Probing active-edge silicon sensors using a high precision telescope

“…(For interpretation of the references to color in this figure caption, the reader is referred to the web version of this paper.) 3 In the center of gravity method the position of the hit on N pixels is calculated after weighting the position of the pixels using their respective charge after the (footnote continued) charge calibration correction with the formula At the edge of the sensor, the efficiency is 4 99% up to 10 μm from the physical edge. The efficiency distribution is fitted with an error function.…”

“…These so-called edgeless sensors are divided into two sub-categories, slim-edge and active-edge. In the case of slim-edge sensors the sensor is diced and passivated closer to the pixel matrix [1] while in the case of the active-edge [2] the sensor is etched and doped 1 [3]. The presence of this doping layer suppresses the surface current between electrodes but also distorts the electric field at the edge of the sensor.…”