Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

Zhang, Zhuqing; Wong, Ching‐Ping

doi:10.1109/tadvp.2004.831870

Cited by 198 publications

(65 citation statements)

References 48 publications

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“…It has been reported that the dielectric strength of an underfill should be above 20 kV/mm [7]. Furthermore, time dependent aging due to applied electric field in the underfill also reported in some literature.…”

Section: Underfill Dielectric Breakdownmentioning

confidence: 87%

Mechanical Modelling of High Power Lateral IGBT for LED Driver Applications

Rajaguru

Bailey

et al. 2018

2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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Abstract-An assembly exercise was proposed to replace the vertical MOSFET by lateral IGBTs (LIGBT) for LED driver systems which can provide significant advantages in terms of size reduction (LIGBTs are ten times smaller than vertical MOSFETs) and lower component count. A 6 circle, 5V gate, 800 V LIGBT device with dimension of 818μm x 672μm with deposited solder balls that has a radius of around 75μm was selected in this assembly exercise. The driver system uses chip on board (COB) technique to create a compact driver system which can fit into a GU10 bulb housing. The challenging aspect of the LIGBT package in high voltage application is underfill dielectric breakdown and solder fatigue failure. In order to predict the extreme electric field values of the underfill, an electrostatic finite element analysis was undertaken on the LIGBT package structure for various underfill permittivity values. From the electro static finite element analysis, the maximum electric field in the underfill was estimated as 38 V/μm. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue failure. These selected underfills have dielectric breakdown higher than the predicted value from electrostatic analysis. The thermomechanical finite element analysis were undertaken for solder bump reliability for all the underfill materials. The underfill which can enhance the solder reliability was chosen as prime candidate.

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Section: Underfill Dielectric Breakdownmentioning

confidence: 87%

Mechanical Modelling of High Power Lateral IGBT for LED Driver Applications

Rajaguru

Bailey

et al. 2018

2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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“…Insertion of underfill in the gap between die and substrate is a popular method to suppress the thermal fatigue degradation. [22][23][24] Underfills are the polymeric composites containing inorganic fillers which provide the bonding of die and substrate so as to redistribute the thermal stresses in solder joints. In recent years, the underfills with high thermal conductivities (κ's) have attracted a lot of research interests due to the increasing demand of heat dissipation of electronic devices.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier’s law of heat conduction at steady-state

Huang

et al. 2018

AIP Advances

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Fourier’s law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ’s) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR’s) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

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“…Significant thermal stresses in the solder joints occur during temperature cycling, ultimately resulting in fatigue cracking and electrical failure. 2,3) To solve this problem, the simplest and most promising method is the underfill process, which fills the gap between the substrate and the chip with an appropriate material. This method can increase the mechanical durability of a flip-chip as well as its electrical quality as the chip size decreases.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Filling Characteristics of a Capillary Driven Underfill Process in Flip-Chip Packaging

Lee

Kim

et al. 2011

Mater. Trans.

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This study investigates the dynamic flow characteristics of capillary-driven underfill flows in a flip chip package. In the present study, we used two different bump arrays using Sn-2.5Ag solder balls with 80 mm and 100 mm diameters on commercially available flip chips, which have different pitches of 150 mm and 180 mm. First, we measured surface tension and viscosity with a rheometer and a tensiometer, respectively, and conducted an experimental visualization of the dynamic filling behavior of the underfill flows. From the captured images, we estimated the filling times, which can be affected by two important factors: bump arrangements and resin viscosities. In addition, we conducted a FVM (finite volume method)-based numerical simulation using commercial CFD code (Fluent v. 6.3.26), and compared its numerical results to both the experimental data and the analytical solutions given by the previous model described by Wan et al. (2005). The numerical predictions and analytical solutions estimating filling time were in good agreement with the experimental data, and the increase in spatial density of solder bumps allowed the flow to fill more slowly due to the increase in flow resistance. We conclude that the non-Newtonian characteristics and bump arrangement are very important factors in the design of flip-chip packaging.

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Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

Cited by 198 publications

References 48 publications

Mechanical Modelling of High Power Lateral IGBT for LED Driver Applications

Mechanical Modelling of High Power Lateral IGBT for LED Driver Applications

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier’s law of heat conduction at steady-state

Dynamic Filling Characteristics of a Capillary Driven Underfill Process in Flip-Chip Packaging

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