Reasoning about time in higher-level language software

Shaw, Alan C.

doi:10.1109/32.29487

Cited by 313 publications

(129 citation statements)

References 13 publications

(1 reference statement)

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“…The WCET of tasks may be easily estimated using the timing analysis presented in [13]. The effect introduced by the cache inclusion is then reduced to know which instructions are loaded and locked in cache and which not.…”

Section: Static Use Of Locking Cachesmentioning

confidence: 99%

On Using Locking Caches in Embedded Real-Time Systems

Campoy

Tamura

Sáez

et al. 2005

Embedded Software and Systems

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Abstract. Cache memories are crucial to obtain high performance on contemporary processors. However, they have been traditionally avoided in embedded real-time systems due to their lack of determinism. Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. This work reviews several techniques developed by the authors to use cache memories in "real" embedded real-time systems, with the ease of use in mind. Those techniques are based on a locking cache, which offers a very predictable behaviour. Both static and dynamic use are proposed as well as the algorithms and methods required to make the schedulability analysis using two different scheduling policies. Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. Finally, a set of statistical analyses compares the locking cache versus a conventional one.

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Section: Static Use Of Locking Cachesmentioning

confidence: 99%

On Using Locking Caches in Embedded Real-Time Systems

Campoy

Tamura

Sáez

et al. 2005

Embedded Software and Systems

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“…One of the earliest works on programming language level timing analysis is the timing schema approach [18]. It is a bottom-up compositional technique which finds the worst-case execution time of a program fragment without considering the contexts in which it is executed.…”

Section: Related Workmentioning

confidence: 99%

“…Due to its inherent importance in embedded system design, timing analysis of embedded software has been extensively studied [6,8,12,13,17,18,20]. Usually this involves (a) a programming language level path analysis to find out infeasible paths in the program's control flow graph, and (b) micro-architectural modeling to take into account the effect of performance enhancing architectural features (such as pipeline, cache and branch prediction).…”

Section: Introductionmentioning

confidence: 99%

Analyzing Loop Paths for Execution Time Estimation

Roychoudhury

Mitra

Negi

2005

Distributed Computing and Internet Technology

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Abstract. Statically estimating the worst case execution time of a program is important for real-time embedded software. This is difficult even in the programming language level due to the inherent difficulty in detecting infeasible paths in a program's control flow graph. In this paper, we study the problem of accurately bounding the execution time of a program loop. This involves infeasible path detection followed by timing analysis. We employ constraint propagation methods to detect infeasible paths spanning across loop iterations. Our timing analysis is exact modulo the infeasible path information provided. Moreover, the analysis is efficient since it relies on memoization techniques to avoid exhaustive enumeration of all paths through a loop. The precision of our timing analysis is demonstrated on different benchmark programs.

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“…But in here presented cache scheme, an instruction will be in cache always, or never will be into, thus its execution time is always constant. To calculate the WCET of a task, the timing analysis presented in [13] is modified to taking account the presence of the locking cache. This analysis is based on the concept of Control Flow Graph of a task.…”

Section: Worst Case Execution Timementioning

confidence: 99%

Schedulability Analysis in EDF Scheduler with Cache Memories

Campoy

Sáez

Perles

et al. 2004

Real-Time and Embedded Computing Systems and Applications

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Abstract. Cache memories can improve computer performance, but its unpredictable behaviour makes difficult to use them in hard real-time systems. Classical analysis techniques are not sufficient to accomplish schedulability analysis, and new hardware resources or complex analysis algorithms are needed. This work presents a comprehensive method to obtain predictability on the use of caches in real-time systems using an EDF scheduler. Reaching a predictable cache, schedulability analysis can be accomplished in a simple way through conventional algorithms. At the moment, this is the first approach to consider cache in this kind of scheduler. The method is based in the use of locking caches and genetic algorithms. Locking caches allows to load and lock cache contents, ensuring its remains unchanged. Genetic algorithms help to select the cache content that offers the best performance. Experimental results indicate that this scheme is fully predictable, and this predictability is reached with no performance loss for around 60% of cases.

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Reasoning about time in higher-level language software

Cited by 313 publications

References 13 publications

On Using Locking Caches in Embedded Real-Time Systems

On Using Locking Caches in Embedded Real-Time Systems

Analyzing Loop Paths for Execution Time Estimation

Schedulability Analysis in EDF Scheduler with Cache Memories

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