Reappraisal of Clock Gating Methods in Different Conditions

Abstract

Nowadays digital concept is used in all fields; every multimedia and DSP based devices are clock based synchronous and asynchronous devices. Clock signals with large frequency are on demand but as frequency of clock increases, power consumption of modules also increases, since power dissipation is directly related to clock frequency. Clock gating method is used to reduce dynamic power, which is due to clock frequency. In this paper review of existing clock gating methods is performed at 90nm technology with different frequency and voltage by applying it on synchronous design like 16-bit FIFO. The proposed architecture is designed using verilog language. The synthesis and simulation work is performed in Xilinx ISE Design suite 14.2 tool and power analysis is done by XPOWER ANALIZER.