Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix

Kumaki, Takeshi; Imai, Yasufumi; Hiramoto, Hirokazu; Koide, Tetsushi; Mattausch, Hans Jürgen

doi:10.1109/mwscas.2010.5548847

Cited by 3 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, few processing elements (PEs) can actually be implemented. For overcoming this parallelism‐related problem, we have developed a massive‐parallel processor based on an SRAM‐embedded matrix architecture (MX‐1) that overcomes the limitations in parallelism of previous architectures. This massive‐parallel SIMD matrix architecture achieves, for example, 40 GOPS (giga operations per second) performance for 16‐bit additions at 200 MHz clock frequency and 250 mW power dissipation in 90‐nm CMOS technology .…”

Section: Massive‐parallel Simd Matrix Architecturementioning

confidence: 99%

“…Since the massive‐parallel SIMD matrix consists of a simple SRAM‐based architecture, the processed data width and the magnitude of parallelism can be changed and optimized in accordance with the application needs. The MX‐1 architecture was introduced for embedded SoC in digital‐convergence mobile devices and has been used to implement multimedia applications, such as DCT processing , JPEG compression , face detection , fast multiplication , image transform , random number , and stream cipher . The MX‐1 has two types of implementation styles, an evaluation board and a simulator.…”

Section: Massive‐parallel Simd Matrix Architecturementioning

confidence: 99%

“…To overcome these serious security‐related problems, we propose an interleaved‐bitslice cipher processing method, which is a software‐based highly parallel block cipher processing method, with a massive‐parallel SIMD matrix architecture (MX‐1) . Since MX‐1 uses a software‐based processing unit for several multimedia algorithm implementations, it is programmable for block cipher processing required by digital‐convergence mobile devices.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

Self Cite

View full text Add to dashboard Cite

This paper presents secure data processing with a massive-parallel single-instruction multiple-data (SIMD) matrix for embedded system-on-chip (SoC) in digital-convergence mobile devices. Recent mobile devices are required to use private-informationsecure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end-user's operation for maintaining the safety condition. To satisfy these security-related requirements, we propose the interleaved-bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massiveparallel SIMD matrix processor (MX-1) for interleaved-bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization-approved block ciphers, a data encryption standard (DES), triple-DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX-1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX-1 results are almost constant for all confidentiality modes. The practical-use energy efficiency of parallel block cipher processing with the evaluation board for MX-1 was found to be about 4.8 times higher than that of a BeagleBoard-xM, which is a single-board computer and uses the ARM Cortex-A8 mobile processor. Furthermore, to improve the operation of a single-bit logical function, we propose the development of a multi-bit logical library for interleaved-bitslice cipher processing with MX-1. Thus, the number of clock cycles is the smallest among those reported in other related-studies. Consequently, interleaved-bitslice block cipher processing with five confidentiality modes on MX-1 is effective for the implementation of parallel block cipher processing for several digital-convergence mobile devices.

show abstract

Section: Massive‐parallel Simd Matrix Architecturementioning

confidence: 99%