Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3 dielectric

Kim, Seyoung; Nah, Junghyo; Jo, Insun; Shahrjerdi, Davood; Colombo, Luigi; Yao, Zhen; Tutuc, Emanuel; Banerjee, Sanjay K.

doi:10.1063/1.3077021

Cited by 911 publications

(921 citation statements)

References 21 publications

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“…The extracted electron carrier mobility was 973 cm 2 V − 1 s − 1 (ref. 28), which was consistent with the graphene grown by the conventional CVD on a Ni surface 2,7 .…”

Section: The Growth Window and Tolerance To Experimental Variationssupporting

confidence: 84%

Rational design of a binary metal alloy for chemical vapour deposition growth of uniform single-layer graphene

et al. 2011

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Controlled growth of high-quality graphene is still the bottleneck of practical applications. The widely used chemical vapour deposition process generally suffers from an uncontrollable carbon precipitation effect that leads to inhomogeneous growth and strong correlation to the growth conditions. Here we report the rational design of a binary metal alloy that effectively suppresses the carbon precipitation process and activates a self-limited growth mechanism for homogeneous monolayer graphene. As demonstrated by an ni-mo alloy, the designed binary alloy contains an active catalyst component for carbon source decomposition and graphene growth and a black hole counterpart for trapping the dissolved carbons and forming stable metal carbides. This type of process engineering has been used to grow strictly singlelayer graphene with 100% surface coverage and excellent tolerance to variations in growth conditions. With simplicity, scalability and a very large growth window, the presented approach may facilitate graphene research and industrial applications.

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“…The extracted electron carrier mobility was 973 cm 2 V − 1 s − 1 (ref. 28), which was consistent with the graphene grown by the conventional CVD on a Ni surface 2,7 .…”

Section: The Growth Window and Tolerance To Experimental Variationssupporting

confidence: 84%

Rational design of a binary metal alloy for chemical vapour deposition growth of uniform single-layer graphene

et al. 2011

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“…Here, μ is the mobility, L and W are the length and width of the channel, respectively, n is the charge-carrier concentration and n res is the residual concentration. 38 We first note that these room temperature mobilities are higher than for similar devices measured on SiO 2 (see refs 9 and 11, and Supplementary Figure S2) and are consistent with previous works using spin valve devices on BN, where a final annealing step is not applied to keep the integrity of the spin-polarized contacts. 8,23,24 It is also important to note that these mobilities are mainly limited by the residues formed during the electrode fabrication process.…”

Section: Spin Transport In Bilayer Graphenesupporting

confidence: 75%

Electronic spin transport in dual-gated bilayer graphene

et al. 2016

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The elimination of extrinsic sources of spin relaxation is key to realizing the exceptional intrinsic spin transport performance of graphene. Toward this, we study charge and spin transport in bilayer graphene-based spin valve devices fabricated in a new device architecture that allows us to make a comparative study by separately investigating the roles of the substrate and polymer residues on spin relaxation. First, the comparison between spin valves fabricated on SiO 2 and BN substrates suggests that substrate-related charged impurities, phonons and roughness do not limit the spin transport in current devices. Next, the observation of a fivefold enhancement in the spin-relaxation time of the encapsulated device highlights the significance of polymer residues on spin relaxation. We observe a spin-relaxation length of~10 μm in the encapsulated bilayer, with a charge mobility of 24 000 cm 2 Vs − 1 . The carrier density dependence on the spin-relaxation time has two distinct regimes; no4 × 10 12 cm − 2 , where the spin-relaxation time decreases monotonically as the carrier concentration increases, and n ⩾ 4 × 10 12 cm − 2 , where the spin-relaxation time exhibits a sudden increase. The sudden increase in the spin-relaxation time with no corresponding signature in the charge transport suggests the presence of a magnetic resonance close to the charge neutrality point. We also demonstrate, for the first time, spin transport across bipolar p-n junctions in our dual-gated device architecture that fully integrates a sequence of encapsulated regions in its design. At low temperatures, strong suppression of the spin signal was observed while a transport gap was induced, which is interpreted as a novel manifestation of the impedance mismatch within the spin channel. INTRODUCTIONGraphene is considered to be a promising spin-channel material for future spintronics applications 1 because of its high-electronic mobility, 2 weak spin-orbit coupling 3,4 and a negligible hyperfine interaction. 5,6 The initial spin transport studies were mainly performed on single-layer 7-10 and bilayer exfoliated graphene, 9,11 and large-area graphene 12-15 deposited on conventional SiO 2 substrates. Although enhanced spin-relaxation times have been reported for bilayer graphene-based devices compared with those based on a single layer, the relatively low spin diffusion constants overall yield a lower spin-relaxation length of only 1-2 μm, 9,11 far below the theoretical predictions. 16 One approach suggested for achieving a longer distance spin communication is to increase the spin diffusion constants by fabricating higher mobility devices. 8,17 For charge transport, it has been shown that the carrier mobility of graphene devices on SiO 2 is mainly limited by interfacial charged impurities, surface roughness, and phonons. [18][19][20] The demonstration of an order-of-magnitude improvement in the mobility of graphene encapsulated between atomically flat, charge trap free boron nitride crystals 21,22 has triggered the recent spin transport studies...

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“…Numerical simulations are carried out based on equation (1). Because charge trapping is much faster compared to the gate voltage ramping speed the details of its time dependence can be neglected.…”

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confidence: 99%

Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

et al. 2014

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ABSTRACT:The interface between graphene and the ferroelectric superlattice PbTiO 3 /SrTiO 3 (PTO/STO) is studied. Tuning the transition temperature through the PTO/STO volume fraction minimizes the adsorbates at the graphene-ferroelectric interface, allowing robust ferroelectric hysteresis to be demonstrated. "Intrinsic" charge traps from the ferroelectric surface defects can adversely affect the graphene channel hysteresis, and can be controlled by careful sample processing, enabling systematic study of the charge trapping mechanism.

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Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3 dielectric

Abstract: We fabricate and characterize dual-gated graphene field-effect transistors (FETs) using Al 2 O 3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al 2 O 3 . Our devices show mobility values of over 8,000 cm 2

Cited by 911 publications

References 21 publications

Rational design of a binary metal alloy for chemical vapour deposition growth of uniform single-layer graphene

Rational design of a binary metal alloy for chemical vapour deposition growth of uniform single-layer graphene

Electronic spin transport in dual-gated bilayer graphene

Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

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