Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits

Hsieh, Cheng-Yun; Wu, Chen-Hung; Huang, Chia-Hsien; Goan, His-Sheng; Li, James Chien Mo

doi:10.1109/dac18072.2020.9218573

Cited by 3 publications

(2 citation statements)

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“…New technologies give rise to new types of defects [1]- [7] that can be modeled as defect-aware [8]- [9], cell-aware [10]- [14] or gate-exhaustive [15]- [19] faults. These types of faults are described by input patterns of subcircuits or cells.…”

Section: Introductionmentioning

confidence: 99%

Increasing the Fault Coverage of a Truncated Test Set

Pomeranz

2022

ACM Trans. Des. Autom. Electron. Syst.

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Defect-aware, cell-aware and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an n -input subcircuit can have up to 2 n faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by T 1 obtained after truncating a larger test set denoted by T 0 . Suppose that the truncation reduces the set of detected faults from the set denoted by D 0 to the set denoted by D 1 . The procedure described in this article modifies the tests in T 1 to gain the detection of faults from D 0 ∖ D 1 , even at the cost of losing the detection of faults from D 1 . The goal is to reduce the fault coverage loss by computing a test set denoted by T 2 that detects a set of faults denoted by D 2 such that | T 2 | = | T 1 | and | D 2 | > | D 1 |. Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.

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Section: Introductionmentioning

confidence: 99%

Increasing the Fault Coverage of a Truncated Test Set

Pomeranz

2022

ACM Trans. Des. Autom. Electron. Syst.

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“…• A probabilistic gradient pruning method is put forward to improve the noise robustness by 5-7% and reduce the #inference on real QC by 2× while maintaining the accuracy. [10]. For example, quantum gates introduce operation errors (e.g., coherent errors and stochastic errors) into the system, and qubits also suffer from decoherence error (spontaneous loss of its stored information) over time.…”

Section: Introductionmentioning

confidence: 99%

QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning

Wang¹,

Li²,

Gu³

et al. 2022

Preprint

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Quantum Neural Network (QNN) is drawing increasing research interest thanks to its potential to achieve quantum advantage on near-term Noisy Intermediate Scale Quantum (NISQ) hardware. In order to achieve scalable QNN learning, the training process needs to be offloaded to real quantum machines instead of using exponentialcost classical simulators. One common approach to obtain QNN gradients is parameter shift whose cost scales linearly with the number of qubits. We present On-chip QNN, the first experimental demonstration of practical on-chip QNN training with parameter shift. Nevertheless, we find that due to the significant quantum errors (noises) on real machines, gradients obtained from naïve parameter shift have low fidelity and thus degrade the training accuracy. To this end, we further propose probabilistic gradient pruning to firstly identify gradients with potentially large errors and then remove them. Specifically, small gradients have larger relative errors than large ones, thus having a higher probability to be pruned. We perform extensive experiments on 5 classification tasks with 5 real quantum machines. The results demonstrate that our on-chip training achieves over 90% and 60% accuracy for 2-class and 4-class image classification tasks. The probabilistic gradient pruning brings up to 7% QNN accuracy improvements over no pruning. Overall, we successfully obtain similar on-chip training accuracy compared with noise-free simulation but have much better training scalability. The code for parameter shift on-chip training is available in the TorchQuantum library.

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