Real-time task scheduling for FPGA-based multicore systems with communication delay

Xu, Jinyi; Li, Kaixuan; Chen, Yixiang

doi:10.1016/j.micpro.2022.104468

Cited by 6 publications

(4 citation statements)

References 23 publications

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“…Refs. [9,10] propose task-level schedulers to accelerate the modules running in parallel on FPGA. HRES is a task partitioning method based on DPR (dynamic partial reconfiguration) [11].…”

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

“…On the other side, task partitioning does not need to deploy FPGA resources to all sub-tasks, because part of sub-tasks entirely runs on the GPU or CPU. [9,10] propose tasklevel schedulers to accelerate the modules running in parallel on FPGA. HRES is a task partitioning method based on DPR (dynamic partial reconfiguration) [11].…”

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

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FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

Wang

Zhou

2022

Electronics

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Accelerators, such as GPUs (Graphics Processing Unit) that is suitable for handling highly parallel data, and FPGA (Field Programmable Gate Array) with algorithms customized architectures, are widely adopted. The motivation is that algorithms with various parallel characteristics can efficiently map to the heterogeneous computing architecture by collaborated GPU and FPGA. However, current applications always utilize only one type of accelerator because the traditional development approaches need more support for heterogeneous processor collaboration. Therefore, a comprehensible architecture facilitates developers to employ heterogeneous computing applications. This paper proposes FLIA (Flow-Lead-In Architecture) for abstracting heterogeneous computing. FLIA implementation based on OpenCL extension supports task partition, communication, and synchronization. An embedded system of a three-dimensional waveform oscilloscope is selected as a case study. The experimental results show that the embedded heterogeneous computing achieves 21× speedup than the OpenCV baseline. Heterogeneous computing also consumes fewer FPGA resources than the pure FPGA accelerator, but their performance and energy consumption are approximate.

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“…Refs. [9,10] propose task-level schedulers to accelerate the modules running in parallel on FPGA. HRES is a task partitioning method based on DPR (dynamic partial reconfiguration) [11].…”

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

Wang

Zhou

2022

Electronics

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“…The scheduling objective is to map tasks onto different Processing Elements (PEs) to satisfy the deadline constraint and the data dependencies while striving to achieve a minimum completion time, known as makespan. Such a problem has been proven to NP-hard [2].…”

Section: Introductionmentioning

confidence: 99%

“…Recently, Zhu et al [13] proposed a real-time task scheduling framework on CPU+FPGA systems, but their work only considered independent tasks. Dependent real-time task scheduling in an FPGA-based multicore setting to minimize the makespan under hardware resource constraints has been investigated in [2]. However, this technique is only evaluated via software simulations using hypothetical FPGA parameters without considering any practical constraints.…”

Section: Introductionmentioning

confidence: 99%

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study

Ahmadi-Pour

Saha

Herdt

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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Heterogeneous platforms, that integrate CPU and FPGA-based processing units, are emerging as a promising solution for accelerating various applications in the embedded system domain. However, in this context, so far, comprehensive studies that combine theoretical features of real-time task scheduling with practical runtime architectural characteristics have mostly been ignored.To fill this gap, in this paper we propose a real-time scheduling algorithm with the objective of minimizing the overall execution time under hardware resource constraints for heterogeneous CPU+FPGA architectures. In particular, we propose an Integer Linear Programming (ILP) based technique for task allocation and scheduling. We then show how to implement a given scheduling on a practical CPU+FPGA system regarding current technology restrictions and validate our methodology using a practical RISC-V case-study. Our experiments demonstrate that performance gains of 40% and area usage reductions of 67% are possible compared to a full software and hardware execution, respectively.

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A Heterogeneous Multicore Co-scheduling Algorithm Based on Multi-characteristic Fuzzy Cluster

Chen,

Chen

2023

Communications in Computer and Information Science

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Real-time task scheduling for FPGA-based multicore systems with communication delay

Cited by 6 publications

References 23 publications

FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study

A Heterogeneous Multicore Co-scheduling Algorithm Based on Multi-characteristic Fuzzy Cluster

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