Real-time scheduling co-processor in hardware for single and multiprocessor systems

Starner, J.; Adomat, J.; Furunas, J.; Lindh, Lennart

doi:10.1109/eurmic.1996.546476

Cited by 11 publications

(19 citation statements)

References 6 publications

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“…The AMU, supporting four accelerators and 32job types (see Section 5.2), required 3300 standard equivalent gates, ignoring the 512 byte RAM . This is considerably smaller than the RTU scheduler [9], whose area, as shown in Table 1 is 25000 gates. The AMU's maximum operating frequency was 526 MHz.…”

Section: Implementation Environmentmentioning

confidence: 89%

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Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Boutellier

Cevrero

Brisk

et al. 2009

2009 IEEE Workshop on Signal Processing Systems

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Handheld devices are expected to start using fine-grained ASIC accelerators to meet energy-efficiency requirements of increasingly complex applications, e.g., video decoding and reconfigurable radio. To avoid overhead, static multiprocessor schedules are preferable for orchestrating fine-grained accelerators. However, as modern applications use accelerators in irregular patterns, static scheduling leads to low hardware utilization.Run-time scheduling for fine-grained accelerators solves the utilization problem, but easily produces significant overhead. We propose an efficient Accelerator Management Unit (AMU) , implemented in hardware. E.g., in video decoding, the AMU takes 3 to 18 cycles to compute a macroblock decoding schedule. The CPU may perform useful work, as the AMU does independent task dispatching.Two experiments are performed, where the AMU is integrated into an FPGA-based multiprocessing prototype system. One experiment does AMU-orchestrated MPEG-4 video decoding and the other demonstrates that the AMU enables low-overhead dynamic scheduling and produces a significant performance advantage over static scheduling.

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Section: Implementation Environmentmentioning

confidence: 89%

“…The real-time service providing co-processor Real-Time Unit (RTU) [9] supports static and priority-based scheduling. The SSCoP real-time scheduling co-processor [8] supports both static and online scheduling with different policies; it assumes that tasks are non-preemptable and have precedence constraints .…”

Section: Related Workmentioning

confidence: 99%

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Boutellier

Cevrero

Brisk

et al. 2009

2009 IEEE Workshop on Signal Processing Systems

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show abstract

“…the maximum number of items that can be sorted). The most popular architectures include FIFO with MUX Tree [10,11,15,21], Shift Registers [18,20,22,23], DP RAM Heapsort [19] and Systolic Array [24][25][26][27][28]33].…”

Section: Related Work On Sorting Architecturesmentioning

confidence: 99%

“…The FIFO approach is the least scalable in terms of critical path length due to the complexity of the MUX Tree part, which contains too long critical path. It is also very inefficient in terms of chip area cost [10,11,15,21].…”

Section: Related Work On Sorting Architecturesmentioning

confidence: 99%

Hardware Dynamic Memory Manager for Hard Real-Time Systems

Kohútka¹,

Nagy²,

Stopjaková³

2019

AETiC

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This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

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“…One solution uses the EDF algorithm too but with the maximum number of tasks being only 64, 25 and the other approach uses priorities instead of deadlines, which is less e±cient for realtime systems in terms of CPU utilization. 26 There are other solutions based on priorities or static scheduling [27][28][29] as well. These solutions are suitable for systems consisting of hard real-time tasks only.…”

Section: Related Workmentioning

confidence: 99%

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Kohútka

Nagy

Stopjaková

2019

J CIRCUIT SYST COMP

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This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

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Real-time scheduling co-processor in hardware for single and multiprocessor systems

Cited by 11 publications

References 6 publications

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Hardware Dynamic Memory Manager for Hard Real-Time Systems

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

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