Real-time performance analysis of multiprocessor systems with shared memory

Abstract

Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new intercore timing dependencies resulting from the common use of the now shared resources. This feedback of system timing on local timing makes traditional performance analysis approaches inappropriate. This article presents a general methodology to model the shared resource traffic and consider its effect on the local task execution. The aggregate busy time captures the timing of multiple accesses to a shared memory far better than the traditional models that focus on the timing of individual events. An iterative approach is proposed to tackle the analysis dependencies that exist in systems with event-driven task activation and dynamic resource arbitration.

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

“…Most analyses consider multi-core systems with a simple bus providing access to a single shared memory [9], [10], [11], [12]. However, contention analysis of clustered many-core platforms has also been explored, as in [13], [14], [15], [16], where the former two are the most relevant for this work, as they focus on Kalray MPPA-256, which is the platform considered in this paper.…”

Right on Time Distributed Shared Memory

“…Sharing memory in real time has been addressed in various contexts, ranging from architectural design and synchronization for real-time shared memories in multi-core machines [34], [35] to real-time replicated databases [7]- [9] and distributed memory. In this section, however, we focus on previous related work in distributed environments (similar to DCSs) rather than on works (i) on architectural memory designs or (ii) on accessing physical shared memory in multi-core machines in real time.…”

A framework for memory contention analysis in multi-core platforms

“…Similarly to our work, most analyses consider multi-core systems with a bus providing access to a shared memory with a single port (Schliecker et al 2010;Schliecker and Ernst 2011;Pellizzoni et al 2010;Dasari et al 2011;Dasari and Nelis 2012;Chattopadhyay et al 2014;Rodrigues et al 2013). However, these works are quite different with respect to the considered task models and scheduling policies for both the tasks themselves and their memory requests.…”

“…list scheduling. The approaches support different task preemption models, ranging from fully preemptive (Schliecker et al 2010;Schliecker and Ernst 2011) to non-preemptive (Dasari et al 2011;Dasari and Nelis 2012;Rosén et al 2007;Chattopadhyay et al 2010), and with limited-preemption at the granularity of TDM time slots as a compromise in between ). Most of these works consider analysis of shared resources as a separate analysis, while (Chattopadhyay et al 2014;Rodrigues et al 2013) integrate it into the WCET estimation tool to exploit information about the execution of the application, such as when memory requests are issued.…”