Real time implementation of MPEG-4 video decoder on ARM7TDMI

Ramkishor, K.; Gunashree, V.

doi:10.1109/isimp.2001.925448

Cited by 15 publications

(7 citation statements)

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“…First, the MPU is relieved and second, the optimised signal processing routines leads to significant decrease of computation times. According to the results of [23] we moved the complex decoding parts to the DSP step-bystep. We started with the inverse DCT (59% of computation time) for the audio and video decoding which still led to an overload of the MPU.…”

Section: Performance Resultsmentioning

confidence: 99%

“…In [23], figures are presented for the speed-up in execution time that a DSP optimised implementation may be expected to achieve compared to a pure implementation on the MPU. According to these figures, DCT may be expected to execute 4.1 times faster, interpolation 7.3 times faster and motion estimation may be expected to accelerate by a factor of 5.2.…”

Section: Input Valuesmentioning

confidence: 99%

See 1 more Smart Citation

Performance evaluation of a DVB-H enabled mobile device system model

Pustina

Schwarzer

Gerharz

et al. 2007

Proceedings of the 6th International Workshop on Software and Performance

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In this experience report, we present experiences we have gained in applying performance engineering techniques during the design of a DVB-H enabled handheld device. The modelling methodology we applied uses UML 2.0 to model the system following a strict separation of architectural and behavioural aspects of the systems. From sequence diagrams and composite structure diagrams, a queueing network is generated for the analysis of the system performance. The configuration of the hardware resources and the resource demands is done using the standard SPT-profile. We describe our implementation and its seamless integration into a UML 2.0 CASE tool. Finally, the paper outlines lessons learnt during the design process which may be used to enhance the methodology.

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Section: Performance Resultsmentioning

confidence: 99%

Section: Input Valuesmentioning

confidence: 99%

Performance evaluation of a DVB-H enabled mobile device system model

Pustina

Schwarzer

Gerharz

et al. 2007

Proceedings of the 6th International Workshop on Software and Performance

View full text Add to dashboard Cite

show abstract

“…The pure software implementation can be found in [5][6][7], where the existing processors such as RISC CPU or DSP are used as the only platform. The design methodology of pure software implementation has the shortest design cycle and is flexible for a wide range of applications.…”

Section: Introductionmentioning

confidence: 99%

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

Wang

Peng

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.

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“…However, an MPEG-4 software video decoder on low-power RISC processors still requires significant amount of computational as well as battery power. The most popular RISC processor in these portable systems is ARM because of its low power consumption and smaller size [10]. Especially in mobile smart phones, the amount of processing power available is limited and has direct impact on the battery life.…”

Section: Introductionmentioning

confidence: 99%

Power Optimization for Mobile MPEG-4 Video Decoder

Pakdeepaiboonpol

Kittitornkun

2005 5th International Conference on Information Communications &Amp; Signal Processing

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Most compiler optimization techniques concern most about speed. In this paper, we present two high-level power/energy optimization methods for ARM-based batterypowered embedded multimedia systems, e.g. mobile phones, pocket PCs, personal multimedia systems, etc. The experiments using MPEG-4 simple profile level 0 (SP@LO) video decoder on ARM920T with two QCIF video sequences 15 fps, 24 kbps show that the proposed techniques can complement the existing speedoriented ones to achieve lower energy/power consumption up to 13% relative to all ARM C++ optimization levels despite the 16-KB instruction and 16-KB data caches of ARM 920T core.

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Real time implementation of MPEG-4 video decoder on ARM7TDMI

Cited by 15 publications

References 0 publications

Performance evaluation of a DVB-H enabled mobile device system model

Performance evaluation of a DVB-H enabled mobile device system model

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

Power Optimization for Mobile MPEG-4 Video Decoder

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