Real-time high-quality stereo vision system in FPGA

Wang, Wenqiang; Yan, Jing; Xu, Ning; Yu, Wang; Hsu, Feng-Hsiung

doi:10.1109/fpt.2013.6718387

Cited by 27 publications

(29 citation statements)

References 11 publications

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“…An explicit comparison with other state-of-theart FPGA-based stereo-vision architecture has not been made since they focus on block-based methods [28][29][30][31]. Even if they provide more dense results, due to their increased complexity, they incur in a greater hardware resources consumption (not including the resources needed for the image pre-processing) [28,52,53].…”

Section: Fpga Subsystem Resultsmentioning

confidence: 99%

“…As aforementioned, most of them focus on the implementation of block-matching algorithms [28][29][30][31] that, in general, are more complex than feature-based algorithms, thus leading to a large resource consumption. Moreover, even if this type of algorithms provides fast and accurate results for a wide range of applications, they cannot be effectively employed in the context of space debris shape reconstruction.…”

Section: Related Workmentioning

confidence: 99%

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A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

Carlo

Prinetto

Rolfo

et al. 2014

EURASIP J. Adv. Signal Process.

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In order to enable the non-cooperative rendezvous, capture, and removal of large space debris, automatic recognition of the target is needed. Video-based techniques are the most suitable in the strict context of space missions, where low-energy consumption is fundamental, and sensors should be passive in order to avoid any possible damage to external objects as well as to the chaser satellite. This paper presents a novel fast shape-from-shading (SfS) algorithm and a field-programmable gate array (FPGA)-based system hardware architecture for video-based shape reconstruction of space debris. The FPGA-based architecture, equipped with a pair of cameras, includes a fast image pre-processing module, a core implementing a feature-based stereo-vision approach, and a processor that executes the novel SfS algorithm. Experimental results show the limited amount of logic resources needed to implement the proposed architecture, and the timing improvements with respect to other state-of-the-art SfS methods. The remaining resources available in the FPGA device can be exploited to integrate other vision-based techniques to improve the comprehension of debris model, allowing a fast evaluation of associated kinematics in order to select the most appropriate approach for capture of the target space debris.

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Section: Fpga Subsystem Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

Carlo

Prinetto

Rolfo

et al. 2014

EURASIP J. Adv. Signal Process.

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“…Therefore, the increase in hardware overhead is unavoidable. Note that rectification is preprocessed before performing disparity estimation, and hardware architecture for the entire disparity estimation usually consumes over 20k LUTs and registers [25,26]. Due to this fact, our proposed hardware architecture shows an acceptable size comparable with disparity estimation.…”

Section: Fpga Resourcementioning

confidence: 99%

Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT

Kim

Oh³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for realtime implementation.

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“…However the concern with the local matching algorithms is its low precision. To mitigate this issue, investigations have been made to implement dedicated hardware architectures of more precise algorithms, such as Semi Global Matching (SGM) [8], [9] and Adaptive Support Weight (ADSW) [10], [11]. For the past few years, hardware implementations predicated on SGM and ADSW algorithms have become the preferred solution towards higher matching precision in embedded vision applications [5], [7], [12], [13].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

Vala

Immadisetty

Acharyya

et al. 2018

IEEE Trans. Circuits Syst. I

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Abstract-Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper we introduce a Discrete Wavelet Transform (DWT) based methodology for a state-of-the-art disparity estimation algorithm, that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba, Venus, Teddy and Cones. The proposed methodology results in improvement of about 44.4% cycles per frame, 52% frames per second and 61.5% and 59.6% LUT and register utilization respectively, compared with state-of-the-art designs.

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Real-time high-quality stereo vision system in FPGA

Cited by 27 publications

References 11 publications

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

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