Real Time Hardware Co - Simulation for Image Processing Algorithms Using Xilinx System Generator

Abstract

The implementation of digital image processing required detailed knowledge of both hardware design and hardware description languages. This paper presents an efficient approach for the implementation of real time hardware digital image processing algorithms without requiring detailed knowledge of hardware design and hardware description languages. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. It focuses on the implementation of an efficient architecture for image processing algorithms like segmentation (threshold) and contrast stretching by using the fewest possible system generator blocks for DSP tool, which integrates itself with the MATLAB based Simulink graphics environment and relieves the user of the textual HDL programming. While Past research has shown that the Image enhancement techniques on FPGA based on the Xilinx System Generator. This study connect between image histogram and Image enhancement techniques depending on the type of enhancement required. This paper describes also the methodology for implementing real-time DSP applications on FPGA and concept of hardware software co-simulation for digital image processing by using the Mathworks model-based design tool Simulink / Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA Virtex5 (XUPV5-LX110T).

Research and Implementation of Digital Image Enhancement Algorithms

“…Certain nonlinear functions like exponential functions and logarithmic functions can be used as mapping functions to implement nonlinear transformation of image gray scale [5] .…”

Acceleration of Images via Software and Hardware using Proprietary Tools & Open Sources for Healthcare Industry

“…FPGA implementation can be done either by using Xilinx System Generator (XSG) or FPGA in the loop (FIL) [10]. Xilinx creates a library in Simulink called Xilinx system generator which generates VHDL code [12].…”