Real-time fault tolerant full adder using fault localization

Gupta, Sonal; Jasuja, Ashish; Shandilya, Rahul

doi:10.1109/sceecs.2018.8546908

Cited by 4 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The subsequent self-fixing circuit involved less territory when contrasted with the past circuit and its offer 100 percent recognition and adjustment of the fault. [2] K. Batish, et. al.…”

Section: _______________________________________________________________________________________mentioning

confidence: 99%

“…A blame tolerant structure empowers a framework to proceed with its expected activity, potentially at a diminished dimension, instead of bombing totally, when some piece of the framework fails. [2] The term is most usually used to depict PC frameworks intended to proceed with pretty much completely operational with, maybe, a decrease in throughput or an expansion accordingly time in case of some incomplete disappointment. That is, the framework overall isn't halted because of issues either in the equipment or the product.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Survey on Fault Tolerance Startgies for Advance Microelectronics Chip

Shekhar¹

2019

IJRITCC

View full text Add to dashboard Cite

In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.

show abstract

“…The subsequent self-fixing circuit involved less territory when contrasted with the past circuit and its offer 100 percent recognition and adjustment of the fault. [2] K. Batish, et. al.…”

Section: _______________________________________________________________________________________mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%