Real Time Edge Detection via IP-Core based Sobel Filter on FPGA

Yaman, Sertaç; Karakaya, Barış; Erol, Yavuz

doi:10.1109/icaaid.2019.8934964

Cited by 14 publications

(7 citation statements)

References 6 publications

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“…By examining the neighboring frequency components within the scalogram, the Sobel filter can identify abrupt changes in the signal's frequency content that often correspond to significant events or features in the signal, such as transients or anomalies. This makes the Sobel edge filter a valuable tool for edge detection in numerous image processing applications [28].…”

Section: Sobel and Wavelet Denoising Filtersmentioning

confidence: 99%

A Hybrid Deep Learning Approach: Integrating Short-Time Fourier Transform and Continuous Wavelet Transform for Improved Pipeline Leak Detection

Siddique,

Ahmad,

Ullah

et al. 2023

Sensors

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A hybrid deep learning approach was designed that combines deep learning with enhanced short-time Fourier transform (STFT) spectrograms and continuous wavelet transform (CWT) scalograms for pipeline leak detection. Such detection plays a crucial role in ensuring the safety and integrity of fluid transportation systems. The proposed model leverages the power of STFT and CWT to enhance detection capabilities. The pipeline’s acoustic emission signals during normal and leak operating conditions undergo transformation using STFT and CWT, creating scalograms representing energy variations across time–frequency scales. To improve the signal quality and eliminate noise, Sobel and wavelet denoising filters are applied to the scalograms. These filtered scalograms are then fed into convolutional neural networks, extracting informative features that harness the distinct characteristics captured by both STFT and CWT. For enhanced computational efficiency and discriminatory power, principal component analysis is employed to reduce the feature space dimensionality. Subsequently, pipeline leaks are accurately detected and classified by categorizing the reduced dimensional features using t-distributed stochastic neighbor embedding and artificial neural networks. The hybrid approach achieves high accuracy and reliability in leak detection, demonstrating its effectiveness in capturing both spectral and temporal details. This research significantly contributes to pipeline monitoring and maintenance and offers a promising solution for real-time leak detection in diverse industrial applications.

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Section: Sobel and Wavelet Denoising Filtersmentioning

confidence: 99%

A Hybrid Deep Learning Approach: Integrating Short-Time Fourier Transform and Continuous Wavelet Transform for Improved Pipeline Leak Detection

Siddique,

Ahmad,

Ullah

et al. 2023

Sensors

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show abstract

“…A logic block comprises three primary elements, namely a look-up table (LUT), a flip-flop (FF), and a multiplexer. FPGAs have the distinguishing characteristic of being reprogramable, allowing for their functionality to be modified by loading new code onto the FPGA [7][8][9][10][11][12][13][14][15].…”

Section: Implementation Toolmentioning

confidence: 99%

“…Vivado constitutes a planning software platform specifically designed for Xilinx FPGAs and is interdependently linked with the layouts of said chips. Consequently, it is unsuitable for deployment with FPGAs furnished by alternative vendors [13][14][15][16][17][18][19] 3.3. Verilog Code for Image Processing.…”

Section: Xilinx Vivado the Vivado Plan Suite Developed Bymentioning

confidence: 99%

Implementation of Image Enhancement and Edge Detection Algorithm on Diabetic Retinopathy (DR) Image Using FPGA

Orthy,

Islam,

Rashid

et al. 2023

IET Circuits, Devices & Systems

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Diabetic retinopathy (DR) is an ocular ailment that may lead to loss of vision and eventual blindness among individuals diagnosed with diabetes. The blood vessels of the retina, a layer of light-sensitive tissue located at the posterior aspect of the ocular globe, are adversely impacted. The identification of DR entails the utilization of retinal fundus images. The detection of any form of abnormality in the eye through raw fundus images poses a significant challenge for medical practitioners. Hence, it is imperative to engage in the processing of fundus images. This paper delineates several image processing techniques for DR images, including but not limited to, manipulation of brightness levels, application of negative transformation, and utilization of threshold operations. It focuses on elucidating the enhancement techniques that pertain to DR images, which aim to optimize the visual quality of said images in order to facilitate more facile disease detection. The process of detecting edges within DR images is also executed by Sobel edge detection algorithm. In order to successfully execute the aforementioned algorithms, expedient and contemporaneous systems are favored to account for the intricacies of the image processing calculations. The exclusive utilization of software techniques in order to fulfill the prerequisites of advanced algorithms presents a significant challenge, owing to the multifarious processes that are involved in their computation, coupled with an exigent requirement for high processing speeds. The proposed model is utilized to articulate a proficient model for the design and execution of field programable gate array (FPGA)-based image enhancement processes along with the Sobel edge detection algorithm upon DR images. Finally, a Internet Protocol chip is developed that can combine multiple image enhancement operations into a single framework with less complexity.

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“…A selection of these significant contributions is discussed herein. The state of the art relating to the FPGA implementation of various digital systems is described in several pieces of literature [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], and a summary is provided in Table 1.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Several pieces of literature discuss the IP core-based designing of essential digital systems and their implementation on contemporary FPGA devices [8][9][10][11][12]. Billmann et al [8] conducted a comprehensive evaluation of the available open-source crypto IP cores.…”

Section: Literature Reviewmentioning

confidence: 99%

Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA

Gupta,

Verma,

Akhter

2023

ISI

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The modular adder, a critical arithmetic component for residue calculations, is explored in this study through its implementation on a field programmable gate array (FPGA), specifically targeting the Xilinx Zynq-7000 family device. Recent literature reveals an innovative combination of parallel prefix addition and flagged prefix addition techniques for the design of the modular adder. The parallel prefix addition, an evolution of the carry look-ahead addition, utilizes the prefix operation, whereas the flagged prefix addition generates a novel set of intermediate outputs, namely flag bits, to execute the increment operation. This paper extends this innovative combination by demonstrating the FPGA implementation of the existing design via two distinct strategies. The first strategy employs a register-transfer level (RTL) description of the design using the very high-speed integrated circuit hardware description language (VHDL), while the second strategy deploys userdefined intellectual property (IP) blocks for the design implementation. FPGA area and power reports are subsequently generated using VIVADO IDE. The RTL approach illustrates an average savings of 14.30% in slice look-up tables (LUTs) utilization and 1.91% in slice flip-flops (FFs) utilization, suggesting its superiority for applications that prioritize area-efficiency. However, the IP modeling approach emerges as crucial for managing the perpetually increasing complexity of system-on-chip (SoC) designs.

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Real Time Edge Detection via IP-Core based Sobel Filter on FPGA

Cited by 14 publications

References 6 publications

A Hybrid Deep Learning Approach: Integrating Short-Time Fourier Transform and Continuous Wavelet Transform for Improved Pipeline Leak Detection

A Hybrid Deep Learning Approach: Integrating Short-Time Fourier Transform and Continuous Wavelet Transform for Improved Pipeline Leak Detection

Implementation of Image Enhancement and Edge Detection Algorithm on Diabetic Retinopathy (DR) Image Using FPGA

Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA

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