Real-Time Computing on Multicore Processors

Sha, Lui; Caccamo, Marco; Mancuso, Renato; Kim, Jung-Eun; Yoon, Man-Ki; Pellizzoni, Rodolfo; Yun, Heechul; Kegley, Russell; Perlman, Dennis; Arundale, Greg; Bradford, Richard

doi:10.1109/mc.2016.271

Cited by 18 publications

(9 citation statements)

References 4 publications

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“…With private banking, the available DRAM banks are partitioned among the available m cores. These assumptions make the considered model compatible with the work in [5]- [7].…”

Section: System Model and Assumptionsmentioning

confidence: 81%

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Agrawal

Mancuso

Pellizzoni³

et al. 2018

2018 IEEE Real-Time Systems Symposium (RTSS)

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One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite significant achievements in the design and analysis of multi-core systems, there is a need for a theoretical framework that can be used to reason on the worst-case behavior of realtime workload when both processors and memory resources are subject to scheduling decisions.In this paper, we focus our attention on dynamic allocation of main memory bandwidth. In particular, we study how to determine the worst-case response time of tasks spanning through a sequence of time intervals, each with a different bandwidth-tocore assignment. We show that the response time computation can be reduced to a maximization problem over assignment of memory requests to different time intervals, and we provide an efficient way to solve such problem. As a case study, we then demonstrate how our proposed analysis can be used to improve the schedulability of Integrated Modular Avionics systems in the presence of memory-intensive workload.

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“…With private banking, the available DRAM banks are partitioned among the available m cores. These assumptions make the considered model compatible with the work in [5]- [7].…”

Section: System Model and Assumptionsmentioning

confidence: 81%

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Agrawal

Mancuso

Pellizzoni³

et al. 2018

2018 IEEE Real-Time Systems Symposium (RTSS)

Self Cite

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“…For example, when two components share a common cache line, the execution of one of them might affect the execution time of the other one, thus jeopardizing the other's capability of meeting timing constraints. Existing work [Ge et al 2019;Sha et al 2016] mitigate this problem by partitioning physical resources properly so as to reduce the non-deterministic temporal behavior due to sharing between components.…”

Section: Overview Of Existing Workmentioning

confidence: 99%

Virtual timeline: a formal abstraction for verifying preemptive schedulers with temporal isolation

Liu

Rieg

Shao

et al. 2019

Proc. ACM Program. Lang.

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The reliability and security of safety-critical real-time systems are of utmost importance because the failure of these systems could incur severe consequences (e.g., loss of lives or failure of a mission). Such properties require strong isolation between components and they rely on enforcement mechanisms provided by the underlying operating system (OS) kernel. In addition to spatial isolation which is commonly provided by OS kernels to various extents, it also requires temporal isolation, that is, properties on the schedule of one component (e.g., schedulability) are independent of behaviors of other components. The strict isolation between components relies critically on algorithmic properties of the concrete implementation of the scheduler, such as timely provision of time slots, obliviousness to preemption, etc. However, existing work either only reasons about an abstract model of the scheduler, or proves properties of the scheduler implementation that are not rich enough to establish the isolation between different components. In this paper, we present a novel compositional framework for reasoning about algorithmic properties of the concrete implementation of preemptive schedulers. In particular, we use virtual timeline, a variant of the supply bound function used in real-time scheduling analysis, to specify and reason about the scheduling of each component in isolation. We show that the properties proved on this abstraction carry down to the generated assembly code of the OS kernel. Using this framework, we successfully verify a real-time OS kernel, which extends mCertiKOS, a single-processor non-preemptive kernel, with user-level preemption, a verified timer interrupt handler, and a verified real-time scheduler. We prove that in the absence of microarchitectural-level timing channels, this new kernel enjoys temporal and spatial isolation on top of the functional correctness guarantee. All the proofs are implemented in the Coq proof assistant.

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“…However, most of that work was focused on single core RTS (that are a majority of such systems in use today). However, multicore processors have found increased use in the design of RTS to improve overall performance and energy efficiency [29,30]. While the use of such processors increases the security problems in RTS (e.g., due to parallel execution of critical tasks) [31] to our knowledge very few security solutions have been proposed in literature [26].…”

Section: Application Specific Checkingmentioning

confidence: 99%

Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems

Hasan¹,

Mohan²,

Pellizzoni³

et al. 2019

Preprint

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We propose a design-time framework (named HYDRA-C) for integrating security tasks into partitioned 1 real-time systems (RTS) running on multicore platforms. Our goal is to opportunistically execute security monitoring mechanisms in a 'continuous' manner i.e., as often as possible, across cores, to ensure that security tasks run with as few interruptions as possible. Our framework will allow designers to integrate security mechanisms without perturbing existing real-time (RT) task properties or execution order. We demonstrate the framework using a proof-of-concept implementation with intrusion detection mechanisms as security tasks. We develop and use both, (a) a custom intrusion detection system (IDS), as well as (b) Tripwire -an open source data integrity checking tool. These are implemented on a realistic rover platform designed using an ARM multicore chip. We compare the performance of HYDRA-C with a state-of-the-art RT security integration approach for multicore-based RTS and find that our method can, on average, detect intrusions 19.05% faster without impacting the performance of RT tasks.

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Real-Time Computing on Multicore Processors

Cited by 18 publications

References 4 publications

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Virtual timeline: a formal abstraction for verifying preemptive schedulers with temporal isolation

Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems

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